Using the Red Pitaya as a pure FPGA

dedicated to the FPGA topics for all Red Pitaya programmers
Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Sun Nov 02, 2014 9:07 pm

There is no document, but you can find out with the resources at hand. Look up the ethernet controller ENET 0 in the PS IP configuration. The ethernet's PHY is connected to MIO16-27,52-53 (see attached picture). Then open the implemented design (implementation needs to be run first) and display the "IO Ports" window. This tells you the pins (sites) the PHY is connected to, as well as the signal names that you can use in your design (FIXED_IO_mio[...]).
The ADC/DAC connections are also shown in the "IO Ports" window (see 2nd pic).
IO config.jpg
IO ports.jpg
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Re: Using the Red Pitaya as a pure FPGA

Post by molinat » Tue Nov 04, 2014 1:59 pm

That clears it all up. Thank you for the help!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Tue Nov 04, 2014 3:50 pm

Glad I could help you get started. Good luck with your FPGA endeavors.

A final note of caution:
If you really want to control the ethernet PHY yourself, you can uncheck ENET 0 in the PS IP configuration and re-generate the blockdesign, then the pins are yours to control.
:!: However, be careful to replicate the IO settings to the letter, otherwise you run the risk of damaging your Red Pitaya. IO settings include voltage level, port direction, port speed, drive strength, etc.

Code safely

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Re: Using the Red Pitaya as a pure FPGA

Post by DrT » Mon Nov 14, 2022 2:09 pm

Dear Support,

I post here because this thread seems the most appropriate.

I also would like to run FPGA but I could keep the OS if you can confirm a couple of points.
The main reason I need the FPGA as free as possible.
So I could use SPI I/O from the FPGA to external boards and leave the OS for initialize the FPGA and (if space left use it for other communications)

_ I wonder how much of the system named ZYNQ7 is needed for the OS to work and it is at all needed in case I want to use SPI to external board/signals. (I could not updaload an image...)

_ I see that in the diagram (ZYNQ7 ) there is an SPI so can I extract its code to use in my application so I can remove anything I do not need?

_ Is the OS needed to set ADC speed/sampling or can I do all from the FPGA?

_what is the best way to sample at 20MHZ instead of 125MZ? can I reduce that on the sampling or I need to downsample within the FPGA?

_is there a way to ask the OS to automatically load an FPGA image?
Many thanks.

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Joined: Tue Nov 16, 2021 11:38 am

Re: Using the Red Pitaya as a pure FPGA

Post by juretrn » Mon Nov 14, 2022 3:23 pm

The bare minimum of FPGA is to generate PS7 via TCL and write a small wrapper for it with DDR RAM signals.
PS is a "hard" ARM core with fixed memory interfaces and shared PS-PL buffers and buses. These are all always there and don't affect the amount of resources used on the FPGA (PL) part.
As far as SPI goes, you can either use the PL GPIO pins with our SPI core or the inbuilt SPI controller on PS7. Both of these are tied to the expansion connector. You can't extract SPI code from PS, but you can use our SPI master core - located in common RTL sources.
The ADC sampling rate is fixed, but the data can be decimated within FPGA. The current oscilloscope application supports averaged or non-averaged decimation. The OS and application don't do anything in that regard except set the appropriate registers as needed.
I don't know how you would set the sampling rate to exactly 20 MHz, you would probably have to use an external clock to do that, let's say 120 MHz and set decimation to 6. Unless you are happy with 20.833 MHz sampling (125/6).
We currently use a script that loads an FPGA design at startup - It just does
/opt/redpitaya/fpga/designName.bit > /dev/xdevcfg.

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