Programming Fpga with CλaSH

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Joined: Wed Jul 08, 2015 8:02 am

Programming Fpga with CλaSH

Post by ralu » Tue Apr 12, 2016 7:33 pm

Clash is programming language that can be compiled in verilog/vhdl and than compiled with Vivado.

I was playing around with and made small project that provides bus core to automatically create interface with both core and client over existing bus infrastructure.

Project is lambdaya-bus and there is short blog about it.

Fell free to post feedback, question or ideas for interesting projects.

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Joined: Thu Jun 16, 2016 9:58 am

Re: Programming Fpga with CλaSH

Post by Tomaok » Mon Jun 20, 2016 2:43 pm

What are the advantages of using CLASH ?

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Joined: Wed Jul 08, 2015 8:02 am

Re: Programming Fpga with CλaSH

Post by ralu » Mon Jun 27, 2016 9:18 pm

Clash is better for multiple reason. It is based and compatible with language Haskell. Haskell is advanced programming language that employs large amount of features that you would expect from state of the art programming language and is full of novel ideas on how modern software should be build. Haskell is mature language and ... er/ provides description of how it is suited for different domains.

One specific domain where Haskell shine by far is programming language design and implementation. There are projects that converts haskell in javascript, JVM, embedded C, python and who knows what more. Clash is language written in haskell that converts in vhdl/verilog or system verilog. Additionally it can be compiled natively as haskell in binary and used as simulation tool or executed like script in REPL. This gives Clash advantage of Haskell ecosystem and ocean of haskell libraries can be used Everything can be used directly in clash, but not everything can be synthesized in hardware. Advantage of having ocean of tools is for example for simulation for drawing graphs to visualize filter response or making bindings for other tools available in specific languages like Python and Matlab. Numerous books, tutorials and scientific papers were written for Haskell and can be used as learning material for both haskell and clash.

Haskell ecosystem enables installing, building testing and deploying software using single tool called stack, (before that it was cabal) and it provides industry grade packet manager for haskell/clash packages.

What makes clash/haskell different as language?
  1. Composability
    Heart of haskell are functions. Haskell is functional programming language and this means that most concepts are modeled composing functions. Larger programs are build by composing smaller programs together. Digital circuits can be modeled as functions. So circuits can be just like functions composed together to make lager circuit.
  2. Type system
    Great part of haskell is type system. Type system is tool that helps in reasoning of how underlying function works. Type system can be also used so that compiler remind us that we want to write program that is not correct. Incorrect programs can be detected during type-checking at compile time and user is encouraged to use type system to enforce rules on what kind of functions can be composed together and to minimize possibility to compose incorrect programs. Type system does not require specifying type signature of every functions because compiler is able to deduce types on its own, but we can write signature as contract to reason how function behaves and how to use this. Type system can be also used to prove properties of programs and to mathematically prove that implementation corresponds to specification. There is great talk from Gabriele Keller on this topic.
  3. Reasoning
    Clash is able to describe similar synchronous digital circuits as verilog/ vhdl or system verilog. It enables reasoning how many registers and gates are and what topology is described. Hard problem that remains is timing optimization and gates placement and this is from my experience more of an art than exact science. Unfortunately I have no expertise in this domain but for my needs I found out that Xilinx places gates together if code is in same module/file. For this reason there is keyword inline availabe in clash that enables expanding funcion in same module instead of creating additional module. Im my case, using only this feature without need to rewrite or moving code around enabled me to reduce timing. Project I am working on is small portion of RedPitaya scope feature. Circuitry was initially designed without using any registry for delay trough whole path from DAC to block RAM but later it turned out that one or two registries as delay in this path were required and enough to work at 125MHz.
  4. Simulation and testng
    Recompilation times in clash are surprisingly fast. It takes few seconds to compile nad check project and fraction of a second to recompile incrementally after small change. Syntactic errors are thrown instantly are descriptive and I think better from what I have experienced from verilog in vivado. It was possible test and simulate, without need of any other tool except clash and REPL that comes with clash. In REPL it takes few seconds to test how function behaves. Clash additionally enables generating testbench code in vhdl/verilog that can be used in vivado or other ASIC/FPGA design tool. I tried that feature but I found using integrated simulator in clash considerably faster. One line of code was frequently enough to test if circuit behaves as expected.
  5. Abstraction
    It is nice to see that using abstractions is for free. It makes more readable, easer to reason about and maintain code but without overhead for sake of using this. There are various thing one can abstract. One simple example is using delayed signal . Default clocked Signal does not provide this info, but when needed DSignal can be used to describe how many clock cycles circuit delays signal. When this kind of abstraction is relevant in particular domain, it can be used to explicitly handle delayed signals. For example composing two circuits when one delays by 7 and other by 2 clocks, we get composition that delays by 9 clocks. This abstraction comes for free in sense that generated circuit has no overhead compared to naive implementation without such type info.
There is no single feature that stands out, but together they build strong foundations for more ambitious projects.

My experiance is that I wouldn't be able to build digital circuit in VHDL or verilog as I was able in clash. It would take more time for similar result. I am also biased in favour of Clash for mentioned reasons and because of that more motivated to program in Clash, because I was looking forward to learn more haskell, clash and digital circuit design. But I am not alone, someone else implemented microprocessor 6502 and he had positive experience too.

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