I think that this topic is the proper one for my issue.
I'm taking a look at this section of code which concerns the changement of FPGA clock and the HP0 bus width, just to understand how it works. It cames from one of the Pavel's projects.
Code: Select all
slcr = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0xF8000000);
axi_hp0 = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0xF8008000);
cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x40000000);
ram = mmap(NULL, 1024*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x1E000000);
// set FPGA clock to 143 MHz and HP0 bus width to 64 bits
slcr = 0xDF0D;
slcr = (slcr & ~0x03F03F30) | 0x00100700;
slcr = 0;
axi_hp0 &= ~1;
axi_hp0 &= ~1;
I've already understand the role of this code, but I would like to have a complete understanding.
First of all, the code maps the memory at a specific address to its corresponding pointer. Taking a look at the UG585 Technical Reference Manual Documentation (page 114), I could check the base address 0XF8000000 corresponds to the System Level Control Registers. Also, I could check the base address 0xF8008000 corresponds to the High Performance Port 0 (HP0).
As the comment itself implies, it changes the FPGA clock by configuring some System-Level Control registers (SLCR Registers) and it changes the HP0 bus width to 64 bits by configuring the corresponding registers.
It is not so difficult to see that variables 'axi_hp0' and 'axi_hp0' correspond respectively to AFI_RDCHAN_CTRL and AFI_WRCHAN_CTRL registers (page 786) and by setting their bit '32BitEn' (bit 0) to zero, it enables the 64-bit bus width for both read and write channels.
My problem lies in understanding the set up of SLCR registers.
As the page 1580 shows the complete description of the register, I've checked that 'slcr' corresponds to the SLCR_UNLOCK register and by writing the value 0xDF0D, it enables writes to the SLCR registers. If I'm correct, 'slcr' corresponds to the register MIO_PIN_12 and 'slcr' corresponds to the register GPIOB_CFG_CMOS25. For the GPIO_CFG_CMOS25, I noted that only allowed values for this register are 0x00000000 (reset value) and 0x0C301100 (normal operation). However, I do not understand the following line 'slcr = (slcr & ~0x03F03F30) | 0x00100700;'
Finally, how is this code able to change the FPGA clock?
Thanks in advance and Happy New Year!!