Red pitaya exited abnormally

[zeroes]

I am trying to create a new project in vivado and write my own code to let the LED blink.
When I run the bitstream, my LED blinked six times and then red pitaya exited abnormally：
cat led_top.bit > /dev/xdevcfg
client_loop: send disconnect: Connection reset
child process exited abnormally

I don't know why this happened, and I've checked my code and don't think there are any errors, can anyone help me? Thank you!

Here is my source:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity led_top is
port (
adc_clk_i : in std_logic;
led : out std_logic
);
end entity led_top;

architecture Behavioral of led_top is
signal clk_div : integer := 0;
begin
process(adc_clk_i)
begin
if rising_edge(adc_clk_i) then
if clk_div < 50000000 then
clk_div <= clk_div + 1;
else
clk_div <= 0;
end if;
end if;
end process;
led <= '1' when clk_div < 2500000 else '0';

end Behavioral;


Constraint file:
set_property IOSTANDARD LVCMOS33 [get_ports {led}]
set_property PACKAGE_PIN F16 [get_ports {led}]

set_property IOSTANDARD LVCMOS18 [get_ports adc_clk_i]
set_property PACKAGE_PIN U18 [get_ports adc_clk_i]

create_clock -period 8.000 -name adc_clk_i [get_ports adc_clk_i]

[redpitaya]

Hello zeroes,
Thank you for writing in the forum.

It is possible that some component must be defined and is not in your case, which crashes the whole FPGA. Have you tried running the bitstream multiple times?

What Red Pitaya OS version are you using?

Regardless, I am moving this into the FPGA topics section.

[zeroes]

Hi, thanks for your reply.

I am using STEMLab 125-14.

I write my code directly in the top module, so I think I don’t need a component. It is also possible that I haven't studied it deeply enough. Can you tell me why it's necessary to use components?

Yes, I have run the bitstream many times, but it has never been successful.

[redpitaya]

I am not 100% sure regarding the extra components, I'll let our FPGA developers answer this one. It was in one of the FPGA tutorials written by Anton Potočnik:
https://antonpotocnik.com/?p=487360,
which we reused here:
https://redpitaya-knowledge-base.readth ... Blink.html

Perhaps you can try modifying the existing LED blink lesson to achieve the wanted functionality. It should include the bare minimum components needed to run the Zynq FPGA on Red Pitaya without crashing (link above). It also includes the necessary definitions.

The downside is that it uses Vivado Blocks and not straight VHDL/Verilog code.