Pulse de-dispersion with red pitaya

[jm]

Good Day,

I am new to pitaya platform and find really useful

I am working on a project that involves correcting pulses that got frequency smeared. This process involves implementing a filter on the FPGA that corrects the smeared pulse train, both the signal and the filter can be defined analytically.

I am thinking about the possibilities of design:

a) Code both the algorithms for the filter and signal, using a platform such as Vivado and create the image file that can loaded by the red pitaya....
or

b) Design both the signal and the filter in C++ and communicate remotely via scpi server?

Which one is best?

Thank You

[Nils Roos]

Good day to you too,

[...] Which one is best?

That mostly depends on your requirements:

You say you want to correct the pulses - does that mean that you want to convert the the filtered data back to analog on the fast analog outputs ?

What range of frequencies are you talking about ? Do you need continuous processing, low latency ?

The scpi-server does not really support continuous sampling, nor continuous (non-periodic) output. If your pulses are isolated occurences, it may be possible to record each one with the scpi-server as a separate triggered event, do the filtering host-side and output the result as a single shot waveform.

If you need continuous processing or a well defined and constant latency between input and output, you'd better look at filtering in the FPGA.

[jm]

Hi Nils,

Thanks for the ever speedy replies!

I am looking towards continuous processing and constant latency, then I reckon implementing the filter on the FPGA will be the better option.

Triggering and filtering on the host side is a tantalizing idea, but if the red pitaya is to act as a pulse watchdog device then filtering needs to happen on the FPGA itself...

The frequency range could be 1300 MHz with 10MHz bandwidth, and the pulse to pulse smearing (what we need to correct for) is in the range of several ms... The corrected pulse train need written out to external file structure...

The process could possibly be: Pulsed signal>ADC>fourier domain>Filter undoes smearing>Time domain>Storage.....

Are there any open source FPGA code simulation packages for Fedora? I reckon Fedora electronics lab?

Thanks

[pavel]

The process could possibly be: Pulsed signal>ADC>fourier domain>Filter undoes smearing>Time domain>Storage.....

Are there any open source FPGA code simulation packages for Fedora? I reckon Fedora electronics lab?

Looking at the description of the problem, I'd say that Xilinx High-Level Synthesis tools could help to solve it. They are not open source but they can be downloaded and used at no cost. Using these tools, the signal processing algorithm could be implemented and simulated in C/C++. All the Xilinx DSP modules (IP cores) are available in form of C/C++ libraries. Here are some interesting links:

http://www.xilinx.com/products/design-t ... esign.html
http://www.xilinx.com/products/design-t ... bpack.html
http://www.xilinx.com/support/documenta ... thesis.pdf
http://www.xilinx.com/support/documenta ... torial.pdf