Hello,
I wanted to create this post in order to ask questions about using Vivado and Verilog. The end goal is to learn about FPGA programming using the Red Pitaya.
Question:
1. I used the FPGA LED tutorial to get started (done with this). Moving on, from the source code repo. RedPitaya, there is no .xpr file. How do you open a project in Vivado in this case?
2. How could you (if possible) convert a verilog module to a block design?
Basic Questions about Vivado/Verilog/RedPitaya
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Re: Basic Questions about Vivado/Verilog/RedPitaya
1. There is a tcl-script in the fpga folder for that purpose (red_pitaya_vivado_project.tcl). You can call this script in the Vivado "Tcl Console" and it will generate the project for you from the sources.
Any changes you make to the generated project in the GUI will only be effective inside the Vivado GUI tools, but not in the Makefile-build.
2. You can package Verilog code inside IP blocks and then use these IPs inside a block design. Here's the relevant documentation from Xilinx.
Any changes you make to the generated project in the GUI will only be effective inside the Vivado GUI tools, but not in the Makefile-build.
2. You can package Verilog code inside IP blocks and then use these IPs inside a block design. Here's the relevant documentation from Xilinx.
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Re: Basic Questions about Vivado/Verilog/RedPitaya
Thanks for the information. Really appreciated!
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Re: Basic Questions about Vivado/Verilog/RedPitaya
Hi,
I also tried to generate a project with Vivado 2016.1, but I get the following error:
ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.1> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
WARNING: [Vivado 12-818] No files matched 'system.bd'
# generate_target all [get_files system.bd]
# read_verilog ./project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v
ERROR: [Common 17-69] Command failed: File 'C:/Users/marco/Documents/RedPitaya/RedPitaya-master/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v' does not exist
how to fix this?
thank you!
I also tried to generate a project with Vivado 2016.1, but I get the following error:
ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.1> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
WARNING: [Vivado 12-818] No files matched 'system.bd'
# generate_target all [get_files system.bd]
# read_verilog ./project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v
ERROR: [Common 17-69] Command failed: File 'C:/Users/marco/Documents/RedPitaya/RedPitaya-master/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v' does not exist
how to fix this?
thank you!
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Re: Basic Questions about Vivado/Verilog/RedPitaya
Hi.
Well, the first error message basically tells it all. Vivado projects are closely coupled to the specific versions of IP blocks that are used in them. If you use a project in a newer version of Vivado, which ships with a different release of one or more of the IPs, you'll have to migrate the IPs in the project to these newer ones first.
If you don't feel confident to do that, I suggest you install the Vivado version that is recommended for the project (2015.4). The different versions can live happily side by side, provided there's enough room.
Well, the first error message basically tells it all. Vivado projects are closely coupled to the specific versions of IP blocks that are used in them. If you use a project in a newer version of Vivado, which ships with a different release of one or more of the IPs, you'll have to migrate the IPs in the project to these newer ones first.
If you don't feel confident to do that, I suggest you install the Vivado version that is recommended for the project (2015.4). The different versions can live happily side by side, provided there's enough room.
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Re: Basic Questions about Vivado/Verilog/RedPitaya
Thank you Niils,
I'm already downlaoding the 2015.4 version.
Is the Vivado version issue, also related to the " could not find system_wrapper.v" error?
thank you!
I'm already downlaoding the 2015.4 version.
Is the Vivado version issue, also related to the " could not find system_wrapper.v" error?
thank you!
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- Joined: Sat Jun 07, 2014 12:49 pm
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Re: Basic Questions about Vivado/Verilog/RedPitaya
The system_wrapper.v (and a lot of other stuff) is automatically generated from the tcl scripts. Processing of the scripts did not even start because of the version mismatch, so all the generated components, including system_wrapper.v, are missing.
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