FPGA Programming: C vs. Verilog

[lhochstetter]

Hi everyone,

it's me once more with more aesthetic related questions:

I. All FPGA code so far is written in Verilog. Aside from Verilog being a / the language to program FPGAs, is there a specific reason (limited functionality, optimization etc.) why Verilog is used instead of writing C Code and using Vivado HLS to pack it into an IP core? (I dare to call C Code more readable than Verilog Code ...)

II. Are you considering at some point a port from Verilog to C?

IMHO it would make the FPGA programming at lot easier to grasp for beginners such as myself ... on the other hand one probably would probably learn Verilog / VHDL / ... to program an FPGA because it could be seen as the more natural approach ...

Just being curious - no Verilog vs. C war intended

[Nils Roos]

Hi,

is there a specific reason (limited functionality, optimization etc.) why Verilog is used instead of writing C Code and using Vivado HLS to pack it into an IP core?

There's a couple of reasons I can think of:

1. HLS didn't exist when the Red Pitaya was developed. The tools that do the C to HDL transformation where introduced in 2014, I believe.
2. The C language works well for expressing algorithms, but lacks concepts that are specific to programmable logic circuits, like clock domains or the use of specific device resources to do a task (ie. PLL, a memory with a certain configuration, etc). Also, it is at least cumbersome to represent the inherent parallelism of logic processes in C.
3. Having a logic design that theoretically does what you want is only part of the work. The tools then need to transform it into an implementation on an actual device in such a way that the circuit meets certain timing requirements. If the tools don't succeed in this, you can give them optimization hints and/or use certain design patterns in the HDL that may help the tools achieve "timing closure". In HLS you are too far removed from the structure of the logic to do that.

Are you considering at some point a port from Verilog to C?

I can not say what is being planned from the Red Pitaya side, but I've got the impression that the focus is more on using standardized IP. You also have to consider that HLS does not integrate easily with the "build everything from source" process.