Unused Pins on ZYNQ FPGA

[tgreen]

I'm determining whether to purchase a Red Pitaya, so perhaps this is a dumb question. The xilinx.com listing for the Z-7010 FPGA states that the chip has a maximum of 100 I/O pins. The Red Pitaya web sites states that only 16 GPIO pins are physically mapped to the extension connectors.

* Is there some way to physically access the apparently unused pins (such as the additional GPIOs) on the FPGA?

* Is it possible in software to address the unused pins using existing Red Pitaya APIs?

* Does the Red Pitaya board provide sufficient amps to drive all of the output pins on the FPGA at once?

* Are there typical testing methodologies for evaluating an FPGA solution that would use pins which aren't connected on the evaluation board (in this case the Red Pitaya)?

[Nils Roos]

System-on-chips are usually designed in such a way that you can switch off their integrated peripherals selectively and use the external pins that were allocated for the peripheral for GPIO instead. It is customary in the industry to give the IO capabilities of a system in terms of maximum number of GPIOs possible.

So the Z-7010 has 100 pins that could potentially be used as GPIO, but if you use the embedded ethernet controller or USB or SD-card interface or ..., the external connections neccessary for these functions reduce the number of pins that are actually free for GPIO.

As it is, all but one or two pins on the Red Pitaya are assigned for a specific function, and the one or two free pins are not accessible, because they are not routed to a place where you could connect to.

There are a few connections on the expansion ports (UART and SPI, amounting to 5 IOs and one output only) and the 8 signals that go to the daisy chain connectors, that you could repurpose for GPIO. So, 13 IOs and one O in addition to the existing 16 GPIOs could be used, but are not supported through the existing RP api. Everything else is hardwired to something already.