Redpitaya Forum

I have found the board definition files for the Red Pitaya at:

https://github.com/RedPitaya/RedPitaya/ ... r/fpga/brd

I have copied them to

/opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1

on my develpment system which is setup according to

http://pavel-demin.github.io/red-pitaya ... t-machine/

When I create a new project in Vivado GUI 2016.3 the Red Pitaya does not show up as Board. Only the three Boards which are provided Xilinx show up.

How can I use the named board definition files in Vivado?

Harald, dl3hm

The TCL Console shows the following error messages:


1) Solution: replace /parameter> with /> in board.xml
CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml, Invalid xml file /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml: unterminated start tag 'parameter'


2) Solution : replace exp_0_io with exp_n_io in board. xml
WARNING: [Board 49-69] Validation failed for board file /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml:
Pin Map file does not provide LOC constraints for exp_0_io[0]COMP : redpitaya.com:redpitaya:part0:0.9

CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml



3) no Solution found => corresponding lines deleted in board.xml
WARNING: [Board 49-69] Validation failed for board file /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml:
Necessary component pins not provided for DAISY_I

CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml


4) Solution: replace connector with switch and adc_clock with system_clock in board.xml
CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml
WARNING: [Board 49-69] Validation failed for board file /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml:
Component Sub Type should be ddr/switch/push_button/lcd/led/ethernet/sfp/sma/mux/reset/system_reset/uart/mgt_clock/system_clock/memory_flash_qspi/memory_flash_bpi/memory/fmc_hpc/fmc_lpc/fmc_lpc_plus/pcie/fixed_io/chip for redpitaya.com:redpitaya:gpio_16bit:0.9

CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml



5) no Solution found => corresponding lines deleted in board.xml
WARNING: [Board 49-69] Validation failed for board file /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml:
Component adc provided for interface adc is not found in list of components on the board.

CRITICAL WARNING: [Board 49-56] Problem parsing board file - /opt/Xilinx/Vivado/2016.3/data/boards/board_files/redpitaya/1.1/board.xml




After I have cured these errors the red pitaya shows up under Create Project in Vivado.

Obviously the cure for error no. 3 and 5 is unsatisfactory.

Harald, dl3hm

Hi Harald,

sorry for the late reply. It seems the board definition files are a work in progress, as you noticed they currently contain malformed xml and other errors. It is uncertain when - or even if - they are going to be completed.
Regarding some of your points:
3) since the daisy chain interface is not implemented in the current releases of the logic, your solution is perfectly acceptable
4) I'm unsure whether 'switch' is the appropriate sub-type for the gpios
5) the pin definition of the adc component seems incomplete, so there is no satisfactory solution at the moment

Is the board definition stable now?

Hello,

I am able to create a Vivado 2018.3 project using the redpitaya board files definition and generate a bitstream but once the design.hdf is exported in sdk, SDK is not happy with it:
ERROR : Failed to openhw "xxx/testBrdRedPitaya/testBrd/testBrd.sdk/design_1_wrapper_hw_platform_0/system.hdf"
java.io.IOException: Command [C 11 xsdb eval "::hsi::utils::openhw C:/xxx/re...] aborted

There is no space or special characters in the path.

I see in the redpitaya github that the board files have not been updated since 4 years and was last reported as buggy:
“brd/redpitaya/1.1 FPGA: Updated board file, still buggy 4 years ago”

i have also tried the SDK export on Windows, Linux with different vivado version up to 2019.1 but without better success (same SDK error)
I am familiar with zedboard and never encountered such problem.

Is any one know about this issue or can help pointing newer redpitaya board files ?

Best regards,
Hervé

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