Greetings!
I recently just got access to a Red Pitaya, and it has proven itself to be an incredible platform.
I'm still fairly new to the FPGA realm, but I had a question when it comes to interfacing the various pins/protocols to your own Verilog modules in the FPGA side. I've installed the RP OS (v0.97-336), tested the example "SPI" C code and ran a few of my own Verilog projects. The questions I have:
1): With the dedicated SPI pins on the E2 connector, how would I go about accessing the information on these pins to the FPGA side?
1a): Would I be able to enable the SPI0/SPI1 MIO pins and connect them to the respective module(s) in the "Block Design"?
---or---
1b): Create my own "MISO"/"MOSI" variables and assign the pin ports (C6, E9...) in the constraints file?
My current working knowledge between the PS/PL is not too advanced, so I may not be aware of any crosstalk challenges between the two. If anyone would happen to have a simple example, that would be invaluable!
Thanks!
SPI Interfacing from Pins to FPGA PLL Modules
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Re: SPI Interfacing from Pins to FPGA PLL Modules
Hello,
If you want to connect a SPI core to the FPGA, you need to select it as EMIO in the Zynq Processing System IP:
You then have access to the SPI pins in the VIvado block design:
You may need to update the device tree in order for Linux to create a corresponding spidev device.
Jean
If you want to connect a SPI core to the FPGA, you need to select it as EMIO in the Zynq Processing System IP:
You then have access to the SPI pins in the VIvado block design:
You may need to update the device tree in order for Linux to create a corresponding spidev device.
Jean
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- Posts: 1
- Joined: Tue Sep 05, 2017 3:25 pm
Re: SPI Interfacing from Pins to FPGA PLL Modules
I appreciate the help Jean!
I took the approach that you mentioned, however I was not able to successfully receive any signal from the "SPI0" from the PS. It appears that I am able to receive data on the Linux environment, but not able to pass it through the PS IP. Perhaps an internal declaration may be mixed up.
In the mean time; I'm going to be utilizing the AXI_Quad_SPI IP for some development.
Thanks again!
I took the approach that you mentioned, however I was not able to successfully receive any signal from the "SPI0" from the PS. It appears that I am able to receive data on the Linux environment, but not able to pass it through the PS IP. Perhaps an internal declaration may be mixed up.
In the mean time; I'm going to be utilizing the AXI_Quad_SPI IP for some development.
Thanks again!
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