Writing AXI stream data to DRAM

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Writing AXI stream data to DRAM

Post by parveen » Sat Nov 18, 2017 9:09 am

I am new to Red Pitaya and FPGAs. I am working on something that needs to transfer data from an AXI stream peripheral to DRAM. Reading through material online, I found that I must use a AXI DMA to convert the stream to memory mapped data that can be written through the HP port. Is this the right way to send AXI stream data to DDR memory? Also, since DRAM is external to FPGA, what are location constraints that need to be put in Constraints file? Where will I find configuration for DDR controller?

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Re: Writing AXI stream data to DRAM

Post by JB » Thu Nov 23, 2017 5:46 pm

You might have a look at the work of Pavel Demin: https://github.com/pavel-demin/red-pita ... s/adc_test

You don't need specific constraints for this purpose. Depending on your speed requirements you could also use a FIFO and the GP-Bus.

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