Improvements to my Lock in Amplifier implementation with PyRPL

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Joined: Thu Jun 28, 2018 1:31 pm

Improvements to my Lock in Amplifier implementation with PyRPL

Post by mkphuthi » Thu Aug 02, 2018 9:22 am

Disclaimer: I am not an expert in electronics so forgive me (and correct me) if I use the wrong terms here and there.

I managed to implement a basic lock-in amplifier using the pyrpl python framework for the RP found by searching PyRPL. This was to perform a frequency sweep on a quartz tuning fork and was able to resolve the resonant frequency up to 1Hz because the Pyrpl module (and I assume the RP) is limited to specifying frequencies only up to 1Hz accuracy.

I used the iq2 module to both produce the reference (The iq module does not allow any other reference to be used) and the driving signal (the output signal was unstable when I used any other signal generator, even the internal pyrpl module). The code I used is shown in the python script below.
resonator_sweep - Copy.txt
I have also attached the results of my frequency sweep, which still fall short of what one would produce with an SR830 and DS345 combination to perform the sweep which would produce very good fits to the Lorentzian plot shown.
I would like to know how I could improve this implementation, hardware, software or otherwise. I am still unsure what the limiting spec is but I suspect it is that the frequency can only be specified with 1Hz accuracy. Is this the limit of the RedPitaya or is it the limit of PyRPL? Would an external clock source help at all with the frequency stability?
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Posts: 12
Joined: Wed Oct 25, 2017 2:51 pm

Re: Improvements to my Lock in Amplifier implementation with PyRPL

Post by Ste_Trat » Thu Aug 23, 2018 8:39 pm

Ok Mr. mkphuthi

never heard of PyRPL, just read a few lines and i must say that things now really start getting interesting...

Thank you for that!

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Joined: Mon Jun 26, 2017 9:22 pm

Re: Improvements to my Lock in Amplifier implementation with PyRPL

Post by mikkelvl13 » Fri Aug 24, 2018 9:57 am

I'm not sure I understand your setup. But have you tried to optimize the iq-parameters?

If not:

As I understand, you use the iq2 to demodulate a modulated signal?
In that case, the phase of the modulation and demodulation signal has to be fixed, and thus you need to use the modulator inside iq2 for both modulation and demodulation (there is a phase drift between the PyRPL asgs and the modulators in the iqs). Also, you need to optimize the phase to compensate any delays in your setup. Finally you should optimize the bandwidth (a LPF) and the acbandwidth (a HPF preventing saturation in the iq-module). For the LPF you can also try out higher order filters supported by the PyRPL iq-moduls.

To optimize the iq-parameters, I recommend the PyRPL GUI! Then you can the optimize until you see nice quadrature signals of the iq.

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