Redpitaya Forum

Hi,

I want to increase the step size (currently 116mHz) of the ASG. As a short test I divided the adc_clk, which is also connected to the ASG, by 128. With this I can output frequencies with a step size of ~8mHz. But using this approach, the clock of the acquisition module and all other modules is also reduced, what is not wanted. Is there a simpler solution that is not affecting other modules? Is it possible to e.g. run the ASG on a slower clock or do all modules need to run on the same clock due to synchronization?

I would be very thankful for any advice.

Thanks

All modules work with one clock frequency.
Thus, we assume that it's impossible to change the frequency of the generator so that it's changed on all modules.