Hello,
the first steps with vhdl, vivado 2019.2 and Red Pitaya are not really obvious !
I was facing the same issue and after reading Anton Potocnik verilog guide I finally got a running example just with vivado gui mode and few vhdl lines (too difficult to learn tcl and vhdl at the same time)
Here is my recipe but CARE : I'm just a beginner !
- create a new empty project, select part xc7z010clg400-1
- create a constraints file to address the led
Code: Select all
set_property IOSTANDARD LVCMOS33 [get_ports led_0]
set_property SLEW SLOW [get_ports led_0]
set_property DRIVE 4 [get_ports led_0]
set_property PACKAGE_PIN J14 [get_ports led_0]
create a vhdl source file which contains our blinking mechanic
Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blink is
port (
clk : in std_logic;
led : out std_logic
);
end blink;
architecture Behavioral of blink is
signal state : std_logic;
-- 100Mhz, 10ns, 1s => 10E8
constant max_count : natural := 10000000;
begin
clk_p : process(clk)
variable count : natural range 0 to max_count;
begin
if rising_edge(clk) then
if count < max_count/2 then
-- 1/2s on
state <= '1';
count := count + 1;
elsif count < max_count then
state <= '0';
count := count + 1;
elsif count = max_count then
state <= '0';
count := 0;
end if;
end if;
end process clk_p;
led <= state;
end Behavioral;
- create a clock design (IP Integrator)
- add ZYNQ7 Processing System IP (press button +)
- connect FCLK_CLK0 to M_AXI_GP0_ACLK
- create HDL Wrapper (right click on block design source)
- add module to block design (right click on vhdl source)
- connect FCLK_CLK0 to RTL clk
- make RTL led external (right click 'make external' on led port : auto connect to our physical led described in constraints.xdc)
- generate bit stream
- scp to Red Pitaya
- cat file.bit > /dev/xdevcfg
Hope it helps
Regards
Pierre Héricourt