RP 122.88 Development Schematic

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Grut3007
Posts: 5
Joined: Wed Mar 04, 2020 10:18 pm

RP 122.88 Development Schematic

Post by Grut3007 » Tue Apr 21, 2020 4:04 pm

Hello,
I was looking at the development schematic for the RedPitaya 122.88MHz board and it showed the ADC with a 122.88MHz clock and the DAC with a 125MHz clock.
http://downloads.redpitaya.com/doc/Cust ... es1%29.PDF

However in the specs for the device it says both chanels are at 122.88MHz.
https://www.redpitaya.com/p52/stemlab-1 ... -kit-basic

Is this a typo in the schematic?

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renegade264
Posts: 13
Joined: Mon Apr 08, 2019 1:08 pm

Re: RP 122.88 Development Schematic

Post by renegade264 » Sun May 03, 2020 10:14 am

I am 99% certain this is a typo in the schematic, they have a huge 122.88 MHz TCXO which makes me unsure of where a 125 MHz could come from as I have not seen any other crystals on the board other than the system 33.333 MHz clock. I would double check this if I had my boards with me, they are unfortunately online remotely :roll: ...

I also have a configuration where the DAC directly goes into the ADC, if the DAC was clocked at 125 MHz and the ADC at 122.88 MHz, I would be seeing a whole heap of frequency components due to intermodulation etc, this is not the case and the FFT output is fairly clean. The DAC is also clocked from the FPGA and operates on a double data rate scheme (data is clocked in on the rising and falling edge), I have checked some of Pavel's projects and he has set the DAC clock at 245.76 MHz. So you can be confident that this is correct and the system is clocked at 122.88 MHz.

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