Redpitaya Forum

I have been successfully(up til now) following red pitaya notes.
There are a few differences in the results, for one, the VIVADO/VITUS suite installs in tools, not opt.
I did not execute the commands in Syntactic sugar for IP cores as these seemed for information only.
I have succeeded in all steps up to the make NAME=led_blinker all which fails.
Can someone help?

I get(just the end of the errors and warnings)
12 Infos, 39 Warnings, 39 Critical Warnings and 2 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2336.898 ; gain = 784.633 ; free physical = 80 ; free virtual = 657
ERROR: [Common 17-39] 'link_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Sun Mar 29 16:35:38 2020...
[Fri May 15 17:47:25 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
# open_run [get_runs impl_1]
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Fri May 15 17:47:25 2020...
Makefile:150: recipe for target 'tmp/led_blinker.bit' failed
make: *** [tmp/led_blinker.bit] Error 1
root@debian:/home/red-pitaya/red-pitaya-notes# ls

Memory (MB): peak = 2336.898

It looks like Vitis/Vivado 2019.2 is consuming more memory than previous versions. So 2048 MB is not enough. Could you try to set the memory size of the virtual machine to 4096 MB?

ERROR: [Common 17-39] 'link_design' failed due to earlier errors.

It would be interesting to see the error messages corresponding to these earlier errors. I think that they can be found in the log files (tmp/led_blinker.runs/*/*.log).

Here is the output copied from the screen attached. I set virtual machine to 4096k before runiing. Thank for looking!!

Thank you for the log file. Here is the first error message from this file (line 312):
So, as I suspected, the virtual machine does not have enough memory for Vitis/Vivado 2019.2. I've just updated the memory requirements in my notes.

I set virtual machine to 4096k before runiing.

Did you restart the virtual machine after setting the memory size of the virtual machine to 4096 MB?

Yes-set to 4096K and restarted virtual machine, but I will double check. It may be that tehre is not enough ram in the host to do this. Will get back to you.

I reset memory again but to 4979K confirmed virtual machine memory correct, and reran make NAME=led_blinker all
I get same errors and the same 39 critical warnings
ERROR: [Common 17-179] Fork failed: Cannot allocate memory

I am at a loss.

Am recloning everything and will start over

I've just followed the instructions and installed a new virtual machine, Vitis, etc. With 4096 MB of memory, Vitis/Vivado doesn't crash. However, I've noticed that building U-Boot now requires bison and flex. I've just added these two packages to the installation scripts. If you've already built a new virtual machine, then you'll need to install these packages manually with the following commands:

I recloned and ran.
Much better result but not perfect. Will try your instruction.

Followed all above. Much different result. Still errors and warnings. I'm not sure its just permissions.

red-pitaya@debian:~/red-pitaya-notes$ make NAME=led_blinker all
mkdir -p tmp
vivado -nolog -nojournal -mode batch -source scripts/hwdef.tcl -tclargs led_blinker

****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source scripts/hwdef.tcl
# set project_name [lindex $argv 0]
# open_project tmp/$project_name.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/red-pitaya/red-pitaya-notes/tmp/cores'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [BD 41-1663] The design 'system.bd' cannot be modified due to following reason(s):
* Block design BD file is read-only. Please check file-permissions.
* Project is read-only. Please run 'save_project_as' before making any change to the bd-design.
* Block design BXML file is read-only. Please check file-permissions.

WARNING: [BD 41-1661] One or more IPs have been locked in the design 'system.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_auto_pc_0
system_sts_0_0
system_concat_0_0
system_dna_0_0
system_ps_0_0
system_ps_0_axi_periph_0
system_pll_0_0
system_const_0_0
system_slice_0_0
system_rst_0_0
system_cntr_0_0

# write_hw_platform -fixed -force -file tmp/$project_name.xsa
INFO: [Vivado 12-4895] Creating Hardware Platform: tmp/led_blinker.xsa ...
WARNING: [Vivado_Tcl 4-413] Exported hardware design may be stale because Block Design is locked for the following reasons
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_auto_pc_0
system_sts_0_0
system_concat_0_0
system_dna_0_0
system_ps_0_0
system_ps_0_axi_periph_0
system_pll_0_0
system_const_0_0
system_slice_0_0
system_rst_0_0
system_cntr_0_0
* Project is read-only. Please run 'save_project_as' before making any change to the bd-design.
* Block design BXML file is read-only. Please check file-permissions.

INFO: [Hsi 55-2053] elapsed time for repository (/tools/Xilinx/Vivado/2019.2/data/embeddedsw) loading 0 seconds
WARNING: [Vivado_Tcl 4-413] Exported hardware design may be stale because Block Design is locked for the following reasons
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_auto_pc_0
system_sts_0_0
system_concat_0_0
system_dna_0_0
system_ps_0_0
system_ps_0_axi_periph_0
system_pll_0_0
system_const_0_0
system_slice_0_0
system_rst_0_0
system_cntr_0_0
* Project is read-only. Please run 'save_project_as' before making any change to the bd-design.
* Block design BXML file is read-only. Please check file-permissions.

WARNING: [Vivado_Tcl 4-413] Exported hardware design may be stale because Block Design is locked for the following reasons
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_auto_pc_0
system_sts_0_0
system_concat_0_0
system_dna_0_0
system_ps_0_0
system_ps_0_axi_periph_0
system_pll_0_0
system_const_0_0
system_slice_0_0
system_rst_0_0
system_cntr_0_0
* Project is read-only. Please run 'save_project_as' before making any change to the bd-design.
* Block design BXML file is read-only. Please check file-permissions.

WARNING: [Vivado_Tcl 4-413] Exported hardware design may be stale because Block Design is locked for the following reasons
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_auto_pc_0
system_sts_0_0
system_concat_0_0
system_dna_0_0
system_ps_0_0
system_ps_0_axi_periph_0
system_pll_0_0
system_const_0_0
system_slice_0_0
system_rst_0_0
system_cntr_0_0
* Project is read-only. Please run 'save_project_as' before making any change to the bd-design.
* Block design BXML file is read-only. Please check file-permissions.

ERROR: [Common 17-99] Failed to open zip archive /home/red-pitaya/red-pitaya-notes/tmp/led_blinker.xsa.
Resolution: Check that you have write permissions at the path specified, and sufficient free disk space.
INFO: [Common 17-206] Exiting Vivado at Wed May 27 17:59:38 2020...
Makefile:146: recipe for target 'tmp/led_blinker.xsa' failed
make: *** [tmp/led_blinker.xsa] Error 1