Vitis 2020.1 Version Missing HSI? Cannot Build!

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tessier5894
Posts: 5
Joined: Wed Sep 08, 2021 10:13 pm

Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by tessier5894 » Wed Sep 08, 2021 10:16 pm

Read your notes about watching carefully during the Xilinx Install. There doesn't seem to be a stand alone SDK in this version. Thus the tool HSI is not installed as a stand alone executable. What am I missing? Screen shot would be helpful.

Thanks,
TomT...

pavel
Posts: 656
Joined: Sat May 23, 2015 5:22 pm

Re: Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by pavel » Thu Sep 09, 2021 6:54 am

tessier5894 wrote:
Wed Sep 08, 2021 10:16 pm
Read your notes about watching carefully during the Xilinx Install. There doesn't seem to be a stand alone SDK in this version. Thus the tool HSI is not installed as a stand alone executable. What am I missing? Screen shot would be helpful.
There is no HSI stand alone executable in Vitis. XSCT should be used to run the HSI commands. More information about XSCT and HSI commands can be found at the following link:
https://www.xilinx.com/html_docs/xilinx ... 44854.html

When I switched from Vivado to Vitis, I had to add the hsi prefix to all of the Tcl commands I use to build FSBL. For example, 'open_hw_design' has become 'hsi open_hw_design' etc. Here is a link to my Tcl script. The command to run this script is

Code: Select all

xsct fsbl.tcl project_name ps7_cortexa9_0

tessier5894
Posts: 5
Joined: Wed Sep 08, 2021 10:13 pm

Re: Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by tessier5894 » Thu Sep 09, 2021 5:57 pm

Pavel,

I just had run GIT on the latest Stable RedPitaya and they mention using Vivado/Vitis 2020.1 but the make file doesn't represent that reality. Did I pull the wrong source?

I was suspecting exactly as you indicated in your scripts, I guess I was surprised that the RedPitaya XilinxFPGA Block Design required 2020.1 but wouldn't complete because this call to HSI hadn't been updated yet.

I am unsure of the process of making recommendations to the RedPitaya team. Is this documented someplace so that I can give them a Stash of the changes I have made to the overall process flow to make this work? Targets are Vivado/Vitis 2020.1 and soon to be 2021.1 as well.

TomT...

pavel
Posts: 656
Joined: Sat May 23, 2015 5:22 pm

Re: Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by pavel » Thu Sep 09, 2021 7:38 pm

I do not use the code from the RedPitaya repository. However, according to the documentation at this link, the recommended versions of the Xilinx tools are the following:
  • Vivado 2020.1
  • SDK 2019.2
I do not know how to contribute changes to the RedPitaya repository. Looking at the number of open issues and pull requests, I would say that the RedPitaya developers do not accept external contributions anymore.

harasaphes
Posts: 3
Joined: Wed Sep 01, 2021 3:04 pm

Re: Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by harasaphes » Sat Sep 11, 2021 8:49 pm

Hi tessier5894,

i have also problems with the official redpitaya documentation and the ecosystem. I tried to do it exactly step by step but at the end there where a lot of critical warnings and errors.
But don't be frustrated. Getting started with the Zynq-7000, SoC with an FPGA (PL) and an ARM core (PS), is not the easiest i think, but the community (with examples, help, e.t.c.) should be big enough!

If I understand this correctly, then the Xilinx SDK is now merched into the Vitis Environment. I'm at the beginning, so i havn't used it, but the process should be nearly the same.

After hours i was frustrated with installing different ubuntu and vivado version e.t.c. to be sucessfull with the redpitaya tutorial.
Then i trired the tutorial from Anton Potočnik. At this time i had also installed on my Windows 10 Vitis with Vivado in Version 2020.1 on my Windows 10 and the acutal OS on my redpitaya. The first example LED blinker worked well with this setup. (SSH: hostname = rp-xxxxxx.local/, user = "root", pw = "root")

If you just want to program the fpga at the beginning, it should be a good possibility to start with the tutorial from Anton Potočnik.
In a few weeks i will start to try all his tutorials. At next i will try Pavel's Environment. It looks more lightweight than the whole redpitaya ecosystem and mybe it's better to learn based on the project from Pavel Denim to build an own whole system.

@pavel: Thank you for your commitment.

Regards,
harasaphes

tessier5894
Posts: 5
Joined: Wed Sep 08, 2021 10:13 pm

Re: Vitis 2020.1 Version Missing HSI? Cannot Build!

Post by tessier5894 » Mon Sep 13, 2021 5:36 pm

Luckily I am not a newbie with Xilinx Embedded Development, just that I stopped doing Zynq embedded design at 2017.2 because of the changes that Xilinx did do the build system for PetaLinux. Now I have to catch back up and it is a little painful.

I am rebuilding a flow like @pavel did completely from scratch -- I was just trying to understand why the RedPitaya folks did the build environment like they did. Not criticizing because I know how painful the Xilinx tool transitions can be. Just wanted to understand the "why"!

@harasaphes your pointers are very helpful! I was able to gleam a few missing pieces from them as well.

I am close to having a flow that I think is stable for my usage and will be testing on hardware this week.

Thanks for all the encouraging words.
TomT...

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