SIGNAL lab 12-250 ports.xdc
Posted: Mon Mar 14, 2022 10:19 pm
Hey all,
I recently got the 250 MSPS device from Red Pitaya. I am working on a research project that requires two reads from the ADC, and three writes to the DAC for each iteration cycle (SPGD for coherent beam combination, to be specific). We are hoping to run this algorithm at about 20 kHz, which given the FPGA should be easy to achieve.
So far, I have the DAC responding to writes (I have a C driver that just adds +1 to a value in a for loop, resulting in "saw-tooth" waves. Anyway, this is not the issue.
I kinda of messed up during the initial developments, and did not realize until later that Frequency counter example was developed for one of the earlier RP devices, which do not follow the same pinnouts as the 250-12. Basically, I am having trouble correctly defining the PACKAGE PINS and IO Standards for each of the ADC inputs. I have tried to use the red_pitaya.xdc from one of the *_250 directories (sdc_250, I think), but I have issues declaring the two 2D array (adc_dat_?_i[*][*]).
Past that, the Customer DOC for the 250-12 says that all the ADC_dat signals are LVDS, but not a single verison of .xdc files in the git repo seem to use that. When I try to declare the IO_standard as LVDS it tells me Bank 34 does not support LVDS. When I try the IO standard found in the red_pitaya.xdc file (DIFF_SSTL18_II), I get bitstream generation errors that some of my ADC data pins are single-ended and that particular standard only supports differential inputs.
Any help would be greatly appreciated, as the 250-12 does not seem to be as well documented/supported as the earlier RP devices. Attached are the .xdc and .tcl files (saved as .txt files) I am using to declare/define my IO ports.
I recently got the 250 MSPS device from Red Pitaya. I am working on a research project that requires two reads from the ADC, and three writes to the DAC for each iteration cycle (SPGD for coherent beam combination, to be specific). We are hoping to run this algorithm at about 20 kHz, which given the FPGA should be easy to achieve.
So far, I have the DAC responding to writes (I have a C driver that just adds +1 to a value in a for loop, resulting in "saw-tooth" waves. Anyway, this is not the issue.
I kinda of messed up during the initial developments, and did not realize until later that Frequency counter example was developed for one of the earlier RP devices, which do not follow the same pinnouts as the 250-12. Basically, I am having trouble correctly defining the PACKAGE PINS and IO Standards for each of the ADC inputs. I have tried to use the red_pitaya.xdc from one of the *_250 directories (sdc_250, I think), but I have issues declaring the two 2D array (adc_dat_?_i[*][*]).
Past that, the Customer DOC for the 250-12 says that all the ADC_dat signals are LVDS, but not a single verison of .xdc files in the git repo seem to use that. When I try to declare the IO_standard as LVDS it tells me Bank 34 does not support LVDS. When I try the IO standard found in the red_pitaya.xdc file (DIFF_SSTL18_II), I get bitstream generation errors that some of my ADC data pins are single-ended and that particular standard only supports differential inputs.
Any help would be greatly appreciated, as the 250-12 does not seem to be as well documented/supported as the earlier RP devices. Attached are the .xdc and .tcl files (saved as .txt files) I am using to declare/define my IO ports.