Boot loop with SDRLab 122-16

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john.schell
Posts: 2
Joined: Fri Mar 04, 2022 2:30 pm

Boot loop with SDRLab 122-16

Post by john.schell » Sat Mar 19, 2022 4:54 pm

Hello,
I have a new SDRLab 122-16 external clock model. I can boot with the supplied SD card image fine, but if I load either the beta or stable SD card image for the 122-16 (loaded with dd or BalenaEtcher), the system continuously re-boots right after displaying OpenBSD secure shell server is loaded or reached target login prompts. I don't know the version of the supplied SD card image, but it appears to be older (there is no led_control command). Is this an issue with the external clock model? I also haven't been successful in getting the webpage to come up. It gets stuck on "generating application list". I tried clearing cache and using chrome and firefox on both windows and a VM Ubuntu.

Thanks for any help.

Best Regards,

John

john.schell
Posts: 2
Joined: Fri Mar 04, 2022 2:30 pm

Re: Boot loop with SDRLab 122-16

Post by john.schell » Sun Mar 20, 2022 1:11 pm

Hello,
I figured out the issue. The external clock drives most of the logic in the FPGA and without it, the system gets stuck in a bootloop. I rebuilt the FPGA image to switch to a local clock and now it doesn't bootloop.

Best Regards,
John

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redpitaya
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Posts: 880
Joined: Wed Mar 26, 2014 7:04 pm

Re: Boot loop with SDRLab 122-16

Post by redpitaya » Wed Mar 30, 2022 1:50 pm

Indeed. We have a big red caution note on the respective product pages
CAUTION: This board needs an external clock signal in order to boot and function!

If a clock signal cannot be provided, you could also chose to perform a reverse external clock mod with the instructions in our online documentation.

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