Redpitaya Forum

Is it possible to sample at 75MHz? Do the ADC and FPGA have to run at the same clock? I have a very good 25, 37.5 or 50MHz clock source. Can the FPGA do the doubling for the ADC?

You can use an external clock with 75 MHz if you have one.

ADC and DAC run on the same clock.

The Red Pitaya Docs have details about how to modify a Red Pitaya STEMlab 125-14 to use an external ADC clock. If you're looking to buy a new Red Pitaya there is a version with the external ADC clock modifications already done to it.

I've not tried an external or FPGA based ADC & DAC clock. I've just stayed with the on board one for now, but it's interesting looking at the docs to think of future project ideas.

The Frequency Counter FPGA lessons 5 originally by Anton Potočnik shows a good basic example of using the ADC and DAC and communication to the Linux CPU of of the board. It shows different clocks for the ADC and FPGA, so you could run the ADC at 75MHz and the FPGA fabric at 150MHZ.

You can even change the FPGA fabric clock while the board is booted using the following Linux terminal commands. The commands need root access. The clock frequency can be set from 100000 to 250000000. 150MHz is used in the example below:

This is great news! The fact that the FPGA clock can go up compared to an external clock. Love that.

Great example!! Thanks

Revisiting this subject again, with somewhat more knowledge on ADC’s and clocks.

I now know I need a low jitter clock more than an accurate clock. Random jitter introduces random noise. Apparent at 125MSPS.

Did anybody measure jitter on the internal clock going through PLL and or FPGA?

I guess the external clock options for low noise 125-14 and 122-16 are feeding the ADC/DAC directly with some analog filtering. Is that correct? Do we have a schematic?

I also guess there is a clock out of the ADC and DAC going to the flag the FPGA data is ready/required. But new to this territory.

Hello ph2thet,

Here is a link to the schematics and the relevant documentation:
https://redpitaya.com/rtd-iframe/?ifram ... dware.html

You can find the schematics on a link under the board specifications.

There you can also find the oscillator datasheet for the boards.

Thank you! Found it.

I am focusing on the 125-14LN. Confused by the three clock sources internal/external/FPGA all tied together. How do you switch between them? You cannot switch the 125MHz off, can you? Also: the FPGA clock output is LVDS. The ADC expects a higher amplitude, right? I am afraid the FPGA clock timing itself can be jittery. Noise by clock jitter can easily at 125MSPS can easily surpass quantization noise hence I just want to be careful here.

Can you explain? Happy to do experiments by the way.

Hello ph2thet,

The clock sources are not tied together. Only two 0R0 are populated depending on the clock source used, as explained here:
https://redpitaya.readthedocs.io/en/lat ... -adc-clock

The external clock needs to be LVDS (same for the SDRlab 122-16 external clock version), as explained here:
https://redpitaya.readthedocs.io/en/lat ... rnal-clock

Please note, we do not advise altering the board because users have reported problems after doing so. Every board made has undergone rigorous testing, which cannot be claimed for modified boards. Any non-Red Pitaya hardware modification will void the warranty, and we cannot guarantee support for modified boards.