Use digital IO while fpga_streaming.bit is loaded?

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QSpin
Posts: 2
Joined: Tue Mar 14, 2023 1:17 pm

Use digital IO while fpga_streaming.bit is loaded?

Post by QSpin » Mon Apr 24, 2023 8:43 am

Dear All, n00b alert, please I need help. I have a STEMLab 125-14 with fpga_streaming.bit loaded and streaming-server running so a client can acquire 20 to 50 MSamples at high speed. At the same time I have another program running on the RP that needs to write to a digital output to operate an actuator. I get a "Bus error" when this program tries to rp_Init(), presumably because rp_Init() is meant to work only with fpga_0.94.bit. My questions: is any of the GPIO on the extension connectors usable while using fpga_streaming? If so, how do I use it? If not, is there any way at all I can get just one digital output going somehow, even if I have to fake it via off-label use of the hardware? Digital output timing is not too critical, + - a few milliseconds would do. Any help would be greatly appreciated.

PS FYI - my OS/ecosystem is 1.04.28

juretrn
Posts: 107
Joined: Tue Nov 16, 2021 11:38 am

Re: Use digital IO while fpga_streaming.bit is loaded?

Post by juretrn » Mon Apr 24, 2023 11:12 am

The FPGA part of streaming app does not yet support GPIO streaming, and neither does SW (as far as I'm aware). This, however, is a feature that we plan on releasing eventually. To do so, you'd have to hack the FPGA sources and SW to add the support for that.
The easiest way would be to add a new register, one more output and then repackage one of the FPGA IPs in stream_app. You can then write that register with your own app if needed.

QSpin
Posts: 2
Joined: Tue Mar 14, 2023 1:17 pm

Re: Use digital IO while fpga_streaming.bit is loaded?

Post by QSpin » Thu Apr 27, 2023 4:33 am

Thanks juretrn, looking forward to that new feature.

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