Red Pitaya ADC/DAC buffers

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Posts: 1
Joined: Thu Aug 21, 2014 11:04 am

Red Pitaya ADC/DAC buffers

Post by dpenev » Thu Aug 21, 2014 11:15 am

Hi All,

We plan to use Red Pitaya for arbitrary signal generation and general signal acquisition.
We may require big memory dept per ADC/DAC channels though.
We saw currently 'generate' and 'acquire' supports up to 16Ksamples/ch
Can this restriction be relaxed?

Also we want to support AWG.
How complex is this to be implemented in the current 'generate' program?


Crt Valentincic
Posts: 67
Joined: Wed May 28, 2014 12:15 pm

Re: Red Pitaya ADC/DAC buffers

Post by Crt Valentincic » Thu Aug 28, 2014 3:24 pm

AWG feature is already implemented in Oscilloscope+Generator WEB application and could be simply implemented also in current generate command line tool.
Actually all you would have to do is load your signal into AWG FPGA module memory buffer as it already done in generate tool for e.g. sine wave signal.
Memory buffer could be much larger if RAM would be used instead of FPGA internal RAM, but at the moment this feature is not implemented yet,
but it can be still done at slower sampling rates, if the CPU is used to stream the data out of the buffer or if you sacrifice one channel and use it's
FPGA memory.

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