Red Pitaya ADC/DAC buffers
Posted: Thu Aug 21, 2014 11:15 am
Hi All,
We plan to use Red Pitaya for arbitrary signal generation and general signal acquisition.
We may require big memory dept per ADC/DAC channels though.
We saw currently 'generate' and 'acquire' supports up to 16Ksamples/ch
Can this restriction be relaxed?
Also we want to support AWG.
How complex is this to be implemented in the current 'generate' program?
Thanks
Dimitar
We plan to use Red Pitaya for arbitrary signal generation and general signal acquisition.
We may require big memory dept per ADC/DAC channels though.
We saw currently 'generate' and 'acquire' supports up to 16Ksamples/ch
Can this restriction be relaxed?
Also we want to support AWG.
How complex is this to be implemented in the current 'generate' program?
Thanks
Dimitar