How to run new bin file on red pitaya

Just about everything about Red Pitaya
Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: How to run new bin file on red pitaya

Post by Nils Roos » Wed Jan 06, 2016 11:54 pm

You can find it here now, but it is not up to date with the currently used Vivado version. You will have to use Vivado 2013.3 or migrate the project yourself if you like to use a newer version.

amin
Posts: 54
Joined: Mon Feb 06, 2017 12:31 pm

Re: How to run new bin file on red pitaya

Post by amin » Mon May 29, 2017 12:52 pm

Nils Roos wrote:You can find it here now, but it is not up to date with the currently used Vivado version. You will have to use Vivado 2013.3 or migrate the project yourself if you like to use a newer version.
Hi nils or all member,

I already install vivado 2015.4 on windows7.
I "open project" the red_pitaya.xpr.
After that, i am doing same step in the tutorial http://blog.redpitaya.com/examples-new/ ... -tutorial/
but vivado is freeze when i click Run Synthesis.
why it is happened.
can you give me easy step by step how to use redpitaya with vivado to generate blink led.

amin
Posts: 54
Joined: Mon Feb 06, 2017 12:31 pm

Re: How to run new bin file on red pitaya

Post by amin » Tue May 30, 2017 2:25 am

I have also tried blink LED using vivado 2015 on from this site http://antonpotocnik.com/?p=487360
I already load project using comman d TCl

Code: Select all

cd C:/Users/chibapc/Documents/GitHub/redpitaya_guide

Code: Select all

source make_project.tcl
from this step is ok no problem
Respond TCL command is like this:

Code: Select all

# set project_name "1_led_blink"
# source projects/$project_name/block_design.tcl
## set part_name xc7z010clg400-1
## set bd_path tmp/$project_name/$project_name.srcs/sources_1/bd/system
## file delete -force tmp/$project_name
## create_project $project_name tmp/$project_name -part $part_name
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
## create_bd_design system
Wrote  : <C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd> 
## source cfg/ports.tcl
### create_bd_port -dir I -from 13 -to 0 adc_dat_a_i
### create_bd_port -dir I -from 13 -to 0 adc_dat_b_i
### create_bd_port -dir I adc_clk_p_i
### create_bd_port -dir I adc_clk_n_i
### create_bd_port -dir O adc_enc_p_o
### create_bd_port -dir O adc_enc_n_o
### create_bd_port -dir O adc_csn_o
### create_bd_port -dir O -from 13 -to 0 dac_dat_o
### create_bd_port -dir O dac_clk_o
### create_bd_port -dir O dac_rst_o
### create_bd_port -dir O dac_sel_o
### create_bd_port -dir O dac_wrt_o
### create_bd_port -dir O -from 3 -to 0 dac_pwm_o
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
### create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
### create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
### create_bd_port -dir O -from 1 -to 0 daisy_p_o
### create_bd_port -dir O -from 1 -to 0 daisy_n_o
### create_bd_port -dir I -from 1 -to 0 daisy_p_i
### create_bd_port -dir I -from 1 -to 0 daisy_n_i
### create_bd_port -dir O -from 7 -to 0 led_o
## set_property IP_REPO_PATHS tmp/cores [current_project]
## update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/cores'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
## set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] [get_bd_cells processing_system7_0]
## set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {cfg/red_pitaya.xml}] [get_bd_cells processing_system7_0]
INFO: [PS7-1] Applying Custom Preset cfg/red_pitaya.xml...
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_0]
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_1]
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_2
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_2]
## set_property -dict [list CONFIG.C_BUF_TYPE {OBUFDS}] [get_bd_cells util_ds_buf_2]
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 c_counter_binary_0
## set_property -dict [list CONFIG.Output_Width {32}] [get_bd_cells c_counter_binary_0]
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0
## set_property -dict [list CONFIG.DIN_TO {26} CONFIG.DIN_FROM {26} CONFIG.DIN_FROM {26} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_0]
## endgroup
## set_property LEFT 0 [get_bd_ports led_o]
## connect_bd_net [get_bd_ports adc_clk_p_i] [get_bd_pins util_ds_buf_0/IBUF_DS_P]
## connect_bd_net [get_bd_ports adc_clk_n_i] [get_bd_pins util_ds_buf_0/IBUF_DS_N]
## connect_bd_net [get_bd_ports daisy_p_i] [get_bd_pins util_ds_buf_1/IBUF_DS_P]
## connect_bd_net [get_bd_ports daisy_n_i] [get_bd_pins util_ds_buf_1/IBUF_DS_N]
## connect_bd_net [get_bd_ports daisy_p_o] [get_bd_pins util_ds_buf_2/OBUF_DS_P]
## connect_bd_net [get_bd_ports daisy_n_o] [get_bd_pins util_ds_buf_2/OBUF_DS_N]
## connect_bd_net [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins util_ds_buf_2/OBUF_IN]
## apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
## connect_bd_net [get_bd_pins c_counter_binary_0/Q] [get_bd_pins xlslice_0/Din]
## connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins c_counter_binary_0/CLK]
## connect_bd_net [get_bd_ports led_o] [get_bd_pins xlslice_0/Dout]
## connect_bd_net [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
## connect_bd_net [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
## generate_target all [get_files  $bd_path/system.bd]
WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
Verilog Output written to : C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote  : <C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd> 
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_processing_system7_0_0'...
WARNING: [xilinx.com:ip:processing_system7:5.5-1] system_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_processing_system7_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_1 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_2_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_2 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_c_counter_binary_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_c_counter_binary_0_0'...
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_c_counter_binary_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_c_counter_binary_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_counter_binary_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_xlslice_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xlslice_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_xlslice_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_0 .
Exporting to file C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system.hwdef
generate_target: Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 912.809 ; gain = 127.191
## make_wrapper -files [get_files $bd_path/system.bd] -top
## add_files -norecurse $bd_path/hdl/system_wrapper.v
## set files [glob -nocomplain projects/$project_name/*.v projects/$project_name/*.sv]
## if {[llength $files] > 0} {
##   add_files -norecurse $files
## }
## set files [glob -nocomplain cfg/*.xdc]
## if {[llength $files] > 0} {
##   add_files -norecurse -fileset constrs_1 $files
## }
## set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset]
## set_property STRATEGY Flow_PerfOptimized_High [get_runs synth_1]
## set_property STRATEGY Performance_NetDelay_high [get_runs impl_1]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
open_bd_design {C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd}
launch_runs impl_1 -to_step write_bitstream
[Tue May 30 09:54:20 2017] Launched synth_1...
Run output will be captured here: C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.runs/synth_1/runme.log
[Tue May 30 09:54:20 2017] Launched impl_1...
Run output will be captured here: C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.runs/impl_1/runme.log
but when i am doing 'generate bitstream' , vivado will always 'running synth_ design' . I am waiting until morethan 30 minute, but this process not finish..

amin
Posts: 54
Joined: Mon Feb 06, 2017 12:31 pm

Re: How to run new bin file on red pitaya

Post by amin » Tue May 30, 2017 1:29 pm

amin wrote:I have also tried blink LED using vivado 2015 on from this site http://antonpotocnik.com/?p=487360
I already load project using comman d TCl

Code: Select all

cd C:/Users/chibapc/Documents/GitHub/redpitaya_guide

Code: Select all

source make_project.tcl
from this step is ok no problem
Respond TCL command is like this:

Code: Select all

# set project_name "1_led_blink"
# source projects/$project_name/block_design.tcl
## set part_name xc7z010clg400-1
## set bd_path tmp/$project_name/$project_name.srcs/sources_1/bd/system
## file delete -force tmp/$project_name
## create_project $project_name tmp/$project_name -part $part_name
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
## create_bd_design system
Wrote  : <C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd> 
## source cfg/ports.tcl
### create_bd_port -dir I -from 13 -to 0 adc_dat_a_i
### create_bd_port -dir I -from 13 -to 0 adc_dat_b_i
### create_bd_port -dir I adc_clk_p_i
### create_bd_port -dir I adc_clk_n_i
### create_bd_port -dir O adc_enc_p_o
### create_bd_port -dir O adc_enc_n_o
### create_bd_port -dir O adc_csn_o
### create_bd_port -dir O -from 13 -to 0 dac_dat_o
### create_bd_port -dir O dac_clk_o
### create_bd_port -dir O dac_rst_o
### create_bd_port -dir O dac_sel_o
### create_bd_port -dir O dac_wrt_o
### create_bd_port -dir O -from 3 -to 0 dac_pwm_o
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
### create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
### create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
### create_bd_port -dir O -from 1 -to 0 daisy_p_o
### create_bd_port -dir O -from 1 -to 0 daisy_n_o
### create_bd_port -dir I -from 1 -to 0 daisy_p_i
### create_bd_port -dir I -from 1 -to 0 daisy_n_i
### create_bd_port -dir O -from 7 -to 0 led_o
## set_property IP_REPO_PATHS tmp/cores [current_project]
## update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/cores'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
## set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] [get_bd_cells processing_system7_0]
## set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {cfg/red_pitaya.xml}] [get_bd_cells processing_system7_0]
INFO: [PS7-1] Applying Custom Preset cfg/red_pitaya.xml...
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_0]
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_1]
## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_2
## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_2]
## set_property -dict [list CONFIG.C_BUF_TYPE {OBUFDS}] [get_bd_cells util_ds_buf_2]
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 c_counter_binary_0
## set_property -dict [list CONFIG.Output_Width {32}] [get_bd_cells c_counter_binary_0]
## endgroup
## startgroup
## create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0
## set_property -dict [list CONFIG.DIN_TO {26} CONFIG.DIN_FROM {26} CONFIG.DIN_FROM {26} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_0]
## endgroup
## set_property LEFT 0 [get_bd_ports led_o]
## connect_bd_net [get_bd_ports adc_clk_p_i] [get_bd_pins util_ds_buf_0/IBUF_DS_P]
## connect_bd_net [get_bd_ports adc_clk_n_i] [get_bd_pins util_ds_buf_0/IBUF_DS_N]
## connect_bd_net [get_bd_ports daisy_p_i] [get_bd_pins util_ds_buf_1/IBUF_DS_P]
## connect_bd_net [get_bd_ports daisy_n_i] [get_bd_pins util_ds_buf_1/IBUF_DS_N]
## connect_bd_net [get_bd_ports daisy_p_o] [get_bd_pins util_ds_buf_2/OBUF_DS_P]
## connect_bd_net [get_bd_ports daisy_n_o] [get_bd_pins util_ds_buf_2/OBUF_DS_N]
## connect_bd_net [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins util_ds_buf_2/OBUF_IN]
## apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
## connect_bd_net [get_bd_pins c_counter_binary_0/Q] [get_bd_pins xlslice_0/Din]
## connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins c_counter_binary_0/CLK]
## connect_bd_net [get_bd_ports led_o] [get_bd_pins xlslice_0/Dout]
## connect_bd_net [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
## connect_bd_net [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
## generate_target all [get_files  $bd_path/system.bd]
WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
Verilog Output written to : C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote  : <C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd> 
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_processing_system7_0_0'...
WARNING: [xilinx.com:ip:processing_system7:5.5-1] system_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'system_processing_system7_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_processing_system7_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_1 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_util_ds_buf_2_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_util_ds_buf_2_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_2 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_c_counter_binary_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_c_counter_binary_0_0'...
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_c_counter_binary_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'system_c_counter_binary_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_counter_binary_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'system_xlslice_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xlslice_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'system_xlslice_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_0 .
Exporting to file C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system.hwdef
generate_target: Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 912.809 ; gain = 127.191
## make_wrapper -files [get_files $bd_path/system.bd] -top
## add_files -norecurse $bd_path/hdl/system_wrapper.v
## set files [glob -nocomplain projects/$project_name/*.v projects/$project_name/*.sv]
## if {[llength $files] > 0} {
##   add_files -norecurse $files
## }
## set files [glob -nocomplain cfg/*.xdc]
## if {[llength $files] > 0} {
##   add_files -norecurse -fileset constrs_1 $files
## }
## set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset]
## set_property STRATEGY Flow_PerfOptimized_High [get_runs synth_1]
## set_property STRATEGY Performance_NetDelay_high [get_runs impl_1]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
open_bd_design {C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/system.bd}
launch_runs impl_1 -to_step write_bitstream
[Tue May 30 09:54:20 2017] Launched synth_1...
Run output will be captured here: C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.runs/synth_1/runme.log
[Tue May 30 09:54:20 2017] Launched impl_1...
Run output will be captured here: C:/Users/chibapc/Documents/GitHub/redpitaya_guide/tmp/1_led_blink/1_led_blink.runs/impl_1/runme.log
but when i am doing 'generate bitstream' , vivado will always 'running synth_ design' . I am waiting until morethan 30 minute, but this process not finish..

amin
Posts: 54
Joined: Mon Feb 06, 2017 12:31 pm

Re: How to run new bin file on red pitaya

Post by amin » Wed May 31, 2017 3:19 am

Nils Roos wrote:If you have LabTools already installed, you should have the promgen utility already. To use it, execute the LabTool settings script (change install location, version number and 32/64 bit as appropriate)
linux:

Code: Select all

source /opt/Xilinx/14.7/LabTools/settings64.sh
windows:

Code: Select all

C:\Xilinx\14.7\LabTools\settings64.bat
Then you should be able to call promgen like this:

Code: Select all

promgen -w -b -p bin -o red_pitaya.bin -u 0 red_pitaya_top.bit -data_width 32
Nils,
Sorry if stupid question because i am confused about how to convert bit to bin, which software was used for execute settings64.sh and settings64.bat.
is it using eclipse or vivado?

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