How to read memory location 0x4060000 in fpga

[rajat]

Hi ,

I have written application in arm to write the data at memory location 0x4060000 and want t o read it in fpga. After reading the int value from 0x4060000 want to set led on red pitaya board. Can any one help me in updating the fpga code to read the memory.

Note: I know how to build the image and start it on the board. Not getting the way yo read the data from memory.

[Nils Roos]

The trick is, 0x40600000 is not actually a memory location, it's just an address that is mapped to the fpga. You need to provide the storage and address decoding logic yourself like this:

1. equip your module with the system bus interface (copy-paste from red_pitaya_hk module declaration)
2. connect your module to the sys_*[6] signals in red_pitaya_top
3. declare some "reg [31:0] mydata;" in your module (this is the storage)
4. copy-paste the block titled "System bus connection" from red_pitaya_hk
5. modify the address decoder logic on sys_addr_i[19:0] so that it uses your mydata-register instead of led_reg and exp_*

I am currently preparing a tutorial that will provide more details and examples for this topic - among other things. So, stay tuned.

[Max]

Hi Nils Roos,

a tutorial on how to integrate a custom FPGA block would be most welcome.

I assume, a simple AXI-lite (as synthesized by Vivado HLS) is more troublesome?

Thanks for the great re-work! Looking forward for its documentation.

Max

[Nils Roos]

Hi Max,

The tutorial was available on the Red Pitaya website for a while, but the 0.94 ecosystem release made it obsolete, so it's no longer there.

I assume, a simple AXI-lite (as synthesized by Vivado HLS) is more troublesome?

The main difficulty with that would be that there is no free AXI master in the new Red Pitaya design to connect your block to.
It's no real trouble, you could insert an AXI interconnect into the path to the XADC wizard IP and you'd have your master interface. The address map configuration will be a bit more convoluted, the GP1 AXI master address range must encompass both, the XADC's and your HLS module's mapping and the split will then be done in the new interconnect.

If you'd rather go the route described previously in this thread, the information is still valid.

Thanks for the great re-work! Looking forward for its documentation.

You're too kind, but I was not involved with the re-work.