Can we reduce ADC resolution from 14 bits to 12 or 8 bits?

[Aragorn2101]

Hi all,

If the ADC resolution could be reduced we could stream high sample rates through network aiding high speed data acquisition. I looked into the ADC on the RedPitaya and I was wondering if we could achieve this in software.

Cheers

[Nils Roos]

The answer is a definite "possibly" !
I'll give the idea a spin in my remote_acquire preview; on the software side it is actually very easy to do, since I already copy the data into a temporary buffer before sending. Question is, will the performance degrade to such a point as to make it moot ?

[Nils Roos]

Tests have shown that a simple "copy every other byte" method before sending is much slower than sending the whole with a linear copy. The measured rates were 7MB/s vs 60MB/s .

This may change if you come up with a very efficient way to transfer every other byte, possibly by using inline assembler.

Honestly, letting the FPGA reduce the width of the samples seems much easier in comparison.

[Aragorn2101]

Hi Nils,

thanks for the replies and for giving it a thought.

Finally, I am happy with the performance of the rp_remote_acquire. As long as the 30 Msps flow in, we are good to go.

Thanks again.
Can't wait to see the final product of the remote_acquire.

Cheers