Bandwidth of the Analog GPIO's

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Joined: Tue Aug 08, 2017 9:27 am

Bandwidth of the Analog GPIO's

Post by paddy » Tue Aug 08, 2017 9:51 am

Hi all,

I will be using Red pitaya STEMlab-14 as a controller. Since i need multiple outputs , i have to use the analog GPIO ports rather than the RF output ports. There are 4 analog GPIO ports and the bandwidth of the each port is not mentioned.The required bandwidth for the process is 100kHz , so need help in getting the max. frequency of each port or even a test program for the same.

Thank you

Posts: 14
Joined: Tue Jul 12, 2016 10:34 am

Re: Bandwidth of the Analog GPIO's

Post by JB » Fri Aug 11, 2017 11:15 am

Hi Paddy,

the slow DACs in the Red Pitaya are realized as PWM DACs. Have a look at [1]. Nils Roos mentions a 100ksps temporal resolution there. Considering the Nyquist theorem this would not be sufficient for your problem. The question is: What degradation in SNR and distortion are you willing to accept? Using only 8 PWM cycles instead of 16 should give you the required bandwidth but at the expense of the SINAD. You could of cause partly prevent that by using an analog filter stage with a steep cut-off.

Another approach might be to use two RPs and synchronize them as in [2].


[2] ... ya-cluster

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