Greetings,
I would like to convert the analog output of a PDB460C-AC photodetector into digital pulses. I use it to track a nearly sinusoidal signal modulation that occurs at ~200 kHz and would like to track it with at least 8 bit precision. Each bit should be fed into a separate coaxial cable, so a parallel interface is required.
I've found an ADC that suits this application but thought of using a Red Pitaya instead, for convenience and agility in future experiments. Before I purchase it, I just want to make sure that Red Pitaya can be used as an ADC that reads an analog input and immediately transmits the readings through its GPIO pins. Is that correct? What latency should I expect between analog readout and GPIO transmission?
Many thanks,
Lior
Using Red Pitaya as a parallel ADC
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Re: Using Red Pitaya as a parallel ADC
Hi Lior,
if you design a straight bypass from the ADC input to the GPIOs into the FPGA, the latency will be about 80ns from time of sampling to data appearing on the GPIO pins. If you plan to use a sampling frequency other than 125MHz, this value will change, because clocked pipeline delays are the biggest part of it.
Regards
Nils
if you design a straight bypass from the ADC input to the GPIOs into the FPGA, the latency will be about 80ns from time of sampling to data appearing on the GPIO pins. If you plan to use a sampling frequency other than 125MHz, this value will change, because clocked pipeline delays are the biggest part of it.
Regards
Nils
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Re: Using Red Pitaya as a parallel ADC
Thanks Nils!
Can you please refer me to some document that explains how to program the FPGA with a straight bypass from the ADC to the GPIOs?
Moreover, if I'd like to normalize the ADC input, dividing it by the maximal value over the past 1000 samples and multiplying by some constant (probably 8192), how much latency will that computation be likely to incur?
I can live with 80 ns latency as long as its jitter won't exceed 13 ns or so.
Thanks a lot,
Lior
Can you please refer me to some document that explains how to program the FPGA with a straight bypass from the ADC to the GPIOs?
Moreover, if I'd like to normalize the ADC input, dividing it by the maximal value over the past 1000 samples and multiplying by some constant (probably 8192), how much latency will that computation be likely to incur?
I can live with 80 ns latency as long as its jitter won't exceed 13 ns or so.
Thanks a lot,
Lior
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- Joined: Sat Jun 07, 2014 12:49 pm
- Location: Königswinter
Re: Using Red Pitaya as a parallel ADC
Scaling the input is a fast operation (1 or 2 cycles) thanks to DSP slices.Moreover, if I'd like to normalize the ADC input, dividing it by the maximal value over the past 1000 samples and multiplying by some constant (probably 8192), how much latency will that computation be likely to incur?
The hidden gotcha is "maximal value over the past 1000 samples" - that is not an easy computation to implement in logic. It would be much easier if you could relax your requirements to something like "the maximum over the samples (n-1)*1000 .. n*1000-1 where n = floor(t / 1000)" - replace the sliding window with a not-so-smoothly-sliding window (jumping window ?^^).
What level of experience with programmable logic would you say you have ?Can you please refer me to some document that explains how to program the FPGA with a straight bypass from the ADC to the GPIOs?
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Re: Using Red Pitaya as a parallel ADC
Good idea! Given that I only try to discern the phase of a sinusoidal oscillation from irrelevant amplitude variations, a jumping window should do the job.It would be much easier if you could relax your requirements to something like "the maximum over the samples (n-1)*1000 .. n*1000-1 where n = floor(t / 1000)" - replace the sliding window with a not-so-smoothly-sliding window (jumping window ?^^).
I'm an electrical engineer so I have some formal knowledge on digital systems, digital and analog circuit design and of course Matlab. But even my Raspberry Pi works on Scratch so I'm practically pretty much of a noob ): Then again, it's about time that I learn how to program an FPGA, and a Red Pitaya could be the right place to start.What level of experience with programmable logic would you say you have ?
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Re: Using Red Pitaya as a parallel ADC
Splendid. You'll need to learn the fundamentals of Verilog, which is a language to describe combinatorial and sequential logic (aka gates and flip-flops). Most of the Red Pitaya's custom logic is written in Verilog. Then you'll need to set up a build environment for the Red Pitaya software. This is described in the main README of the Red Pitaya github repository. Acquiring a passing familiarity with the Vivado tools is also helpful.I'm an electrical engineer so I have some formal knowledge on digital systems, digital and analog circuit design
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Re: Using Red Pitaya as a parallel ADC
Thanks a lot Nils! We'll place an order for three calibrated Pitayas this week (:
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