Red Pitaya synchronization

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vil_magsumov
Posts: 1
Joined: Wed May 04, 2016 11:22 am

Red Pitaya synchronization

Post by vil_magsumov » Wed May 04, 2016 11:28 am

Hello to everyone!
I want to synchronize multiple cards Red Pitaya. How can I do it? One of the cards will ba a master others will be slave.
Thank you

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Red Pitaya synchronization

Post by Nils Roos » Sat May 07, 2016 12:00 am

What kind of synchronisation do you have in mind? Eg. long term acquisition at a synchronized sampling rate, synchronized triggering for short term recording, ... ?

You can modify a Red Pitaya for external sampling clock input with some soldering (see here).

williolic
Posts: 3
Joined: Wed Apr 20, 2016 11:34 am

Re: Red Pitaya synchronization

Post by williolic » Mon Jul 04, 2016 3:28 pm

Hi all,

I would like to synchronize the outputs of two red pitayas. My aim is to have 4 signals at the same frequency with a dedicated phase shift.
The problem is the synchronization of the DACs.
I saw that it is possible to use an external ADC clock but this seems to be an amount of effort and I didn't find a detailed description how I could implement this. For this reason I would like to know if this is really the only and/or the best solution for my problem.

I'm looking forward to your help. Thanks in advance!

Best
Oli

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Red Pitaya synchronization

Post by Nils Roos » Mon Jul 04, 2016 4:21 pm

Hi Oli,

there is no out-of-the-box way to synchronize two Red Pitayas in the way you want.

I see three possible avenues of approach:
1. Change one or both RPs to external ADC clock and synchronize the whole signal path that way. Use one of the RPs as master clock or tie both to an external clock source.
2. Change the programmable logic to accept an alternate clock as the DAC clock, eg. from the daisy chain connectors or GPIOs.
3. Use the ADC of the second RP to measure the signals from the first and adaptively adjust its own generator parameters.

Option 1 requires some soldering on your RPs, while option 2 requires changes to the FPGA design. Option 3 can be done on the application side, but will not achieve the same level of synchronicity as the other two.

williolic
Posts: 3
Joined: Wed Apr 20, 2016 11:34 am

Re: Red Pitaya synchronization

Post by williolic » Tue Jul 05, 2016 7:13 am

Hi Nils,

thank you very much for the quick response and the excellent summary.
I think I will try to implement the first solution.
I know it requires soldering as it can be seen here http://wiki.redpitaya.com/index.php?tit ... _ADC_clock
I would prefer to use one of the RPs as master clock. There still remains three questions for me:
1. Is in this case soldering just necessary at one of the RPs?
2 Which pins of the two RPs must be connect?
3. Must there still made some configurations on the software-level for this solution?

Best
Oli

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Red Pitaya synchronization

Post by Nils Roos » Tue Jul 05, 2016 1:04 pm

1. Is in this case soldering just necessary at one of the RPs?
2 Which pins of the two RPs must be connect?
When proposing to use one of the RPs as master clock source, I neglected to consider that the RP's logic currently doesn't have a clock output. You'd have to route the ADC clock in the logic design to the GPIOs and connect them to the external clock input of the second RP. So the first RP would need some slight modifications to its programmable logic and the second would need to be resoldered for external clock source.
3. Must there still made some configurations on the software-level for this solution?
You need to make provisions to start all signals simultaneously. This is best done by setting them all to external trigger and wire them up with a GPIO on one of the RPs that you then assert in software. How to go about that depends on the method you plan to use to control the whole setup (eg. web-app, RP api, LabView, ...).

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