What are the SFSPI connections in the schematic

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Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

What are the SFSPI connections in the schematic

Post by Nils Roos » Sat Jul 30, 2016 11:59 am

Xyefa asked on github:

Looking at the picture below, I just want to clarify one more thing:

So SPI0 are the pin PS_MIO1_500 to PS_MIO6_500 (with 3 chip selects???)?

And SPI1 are the pins PS_MIO10_500 to PS_MIO13_500? And these are the ones that are mapped on the header pins?
schematic.png
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Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: What are the SFSPI connections in the schematic

Post by Nils Roos » Sat Jul 30, 2016 12:06 pm

SPI1 is the interface accessible on E2, correct.

The SFSPI* lines belong to a Q(uad)SPI flash interface (4 data lines, 1 CS), and are routed to the unoccupied place in the middle between ZYNQ, ADC, DRAM and E2.
extFlash.png
I suppose this interface was meant to provide an on-board bootmedium, but is not used in Red Pitayas of v1.0 and v1.1, although the device is activated in the PS7 configuration.

SPI0 used to be mapped to EMIO in the older (<0.94) versions, but there was never anything connected to it in the PL.
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