Accessing the 2nd fast analog output?

[blevlab]

I'm new to programming the FPGA on Red Pitaya and I'm confused about the 2nd fast analog output. In the constraints file only one channel of the DAC output is defined, and in the v.1.0.1 schematic, the inputs to channel B of DAC are all crossed out. Does this mean the 2nd analog output is not functioning? If not, how can I access it? Thanks a lot.

[Nils Roos]

The data transfer to the DAC works in double data rate mode, where channel A data is transmitted on the rising clock edge and channel B data on the falling edge. This is handled by the DDR output buffers oddr_dac_dat - current design / new design.