ADC external clock

[mimok]

Hi everybody,

I'm wondering if it is possible to use an external clock as ADC clock. I saw in the manual that one of the connector own two pins named 'fast ADC clk+' and fast ADC clk-'. Does this differential input can be used as an ADC clock input and how can I use it?

Best regards

[Crt Valentincic]

Yes it is possible. ADC can be clocked from on board 125MHz XO oscillator, FPGA or from external pins. Switching from one source to another is done by moving 2 zero ohm resistors (Moving R25, R26 to position R23, R24). http://wiki.redpitaya.com/index.php?tit ... _ADC_clock

[Arne]

I had a question along the same line.

Are schematics available to look at?

I presume that this would affect the clock for the entire board (FGPA, ADC, DAC)?

Thanks
Arne

[Nils Roos]

Changing the ADC encoding clock source would affect the ADC, DAC and all the data processing blocks inside the FPGA.

I would also like to be able to peek at the RedPitaya schematics from time to time, but we don't really need to in this case.
The signal flow outside of the FPGA is quite simple, the ADC data output clock is derived from the encoding clock, and this clock output feeds into the FPGA and is used as the clock source for all data processing (wire "adc_clock" in red_pitaya_top) and also for generating the DAC and daisy-chain clock outputs.
All other processing inside the FPGA - mainly the interface to the ARM cores - runs from a processor generated clock source, and is by design asynchronous to the ADC clock.

This means that there should be no glitches if you switch to a different clock source for the ADC, but bear in mind that the whole input and output signal paths and the downstream connection via daisy chain run at this clock.

[sa-penguin]

I will admit - the idea of a different clock rate is appealing. 120MHz is easier to divide or decimate.
A TCXO (temperature compensated for lower drift) could be put on an external board, plugged into E2, and allowed to warm up. Placing it near the FPGA heatsink could actually be an advantage.

However, the prospect of desoldering and moving R25 and R26 fills me with horrors. Neither my eyesight nor my hands are up to the task. Oh well.
If ever there is a Yellow Pitaya this part of the design could be modified. A Double Pole Triple Pole Slide Switch comes to mind: http://www.mouser.com/pdfdocs/Tyco-Slide.pdf

[Dr_Radar]

Is it possible to use a 10 MHz external clock input, instead of the built in 125 MHz clock or does the external clock need to be 125 MHz also?

[Nils Roos]

Let me put it this way:

1. The ADC supports sampling frequencies of 1MHz - 125MHz
2. I have no way of testing the FPGA for support of lower sampling frequencies, but there are some things that will have to be addressed, like the PLL generating the DAC and daisy-chain clocks

So to answer your question whether it's possible to use an external ADC clock of 10MHz: probably yes, but no guarantees.