External ADC

[talis]

Whilst RedPitaya offers digital costas & demodulation by FPGA .. the 8bit converter limits dynamic range for signals.
Given the advances possible using external DDS / & 14bit A/D may i ask Pavel or Assoc to adapt custom FPGA module (RT Linux environ , MIPS coprocessor) for AD9854 as a Digit PLL control for a Lo driving a 14bit A/D baseband converter ( sampling 3 GSPS ) at 110MHz - 300MHz input .. All hardware is ready built as modular , control of 9854 thru SPI JTAG interface and Freq Accum offsets .. Nils may find interest ? No pressure.. Extended time.

[pavel]

8bit converter limits dynamic range for signals

Normally, Red Pitaya's ADC is 14-bit. So, this part is not very clear for me.

AD9854 as a Digit PLL control for a Lo

AD9854 can be easily controlled via the on-board SPI port (connector E1, pins 3-5).

Some examples of a code controlling AD9854 can be found in the SDR1000 code. For example, at the following link:
https://github.com/alexlee188/ghpsdr3-a ... src/common

[Nils Roos]

Just a random question:
Wasn't talis the name of one of those experimental chatbots?

[lhochstetter]

@Nils that'd be kinda creepy and hilarious at the same time.

[talis]

Very funny.. an experimental bot is hardly the AI class i was hoping. Back on topic.. the limited hardware disclosure led to an 8 bit reference.

however, on-chip converters suffer unacceptable cross-talk due to chip geometry.. current needs require a synchronous pair of AD6676 converters
for bond resonance studies in live cell phosphorylation whilst observing ion exchange in mitochondria focused by an electron beam, of an inhouse electronmicroscope ..


Todays lineup of DDS solutions provides wide precise excitation modulation, to that end a 9959 usefully upconverts modulation to a bond resonance band of interest .. I realize u are busy with the Pitaya , a most useful academic tool .. yet FPGA control of 6676 eval module via a Zynq MPSoC UltraScale+ with MALI graphics accelerator, helps us deliver image transcoding from the 6676 conversion input into the MPSoC FPGA digital demodulation .. As u already deal with 14 bit FPGA demodulation , this is not such a difficult port .. I am flexible with the FPGA , it may be an FMC host , the FMC interface to the 6676 being well established thru HSC-ADC - EVALEZ.. The issue with that excellent MATLAB driver PC software is it does not allow modulation control of the 9959 and ADF4351 .. and there is no MALI core on the FPGA ..

Maybe that clears the air .. Maybe there is some interest in this .. once a competent state machine prgmer appears .. Zynq , Imagination , pic a preferred FPGA solution .. .. email did not receive on yor reply .. thus lateness .. also log in drops out , very annoying.. can we switch off all but plain text ?

Cheers, Rus

[talis]

Patel , thanks for the link , there are a few German boffins i met who also gave an SPI interface thru JTAG
The point for the 9854 was to provide an agile upconverted sampling clock to the 6676 able to sweep a few MHz minimising jitter in the 6676 onchip synth .. so its a bit more than just being able to steer the 9854 thru SPI . This couples the digitising performance to real time dig demodulation in the loop while shifting both the Rx clock and stimulus RF. As i have all the modules and external mixers ( not a difficult acquisition ) there remains the task of selecting FPGA module ( per above) & writing the demodulator lock-in routine of the faint return signal (unique acquisition not practiced, as all my methods) A task made easy by same location Tx / Rx . Care to quote in stages ?
Not difficult.. with the building blocks avail & bonus of complete flexiblity in the digital domain. Regards,
Rus

[pavel]

AD6676 is indeed a very interesting ADC. Its JESD204B interface requires an FPGA with 6.25Gb/s or faster transceivers and a JESD204B IP core. If you also need the MALI graphics accelerator, then it's clearly out of reach of the Red Pitaya board.

Here is a link to the JESD204B IP core provided by Xilinx:
https://www.xilinx.com/products/intelle ... sd204.html
http://www.digikey.com/product-search/e ... SD204-SITE

And here is a board that matches quite well your requirements:
https://www.xilinx.com/products/boards- ... es2-g.html
http://www.digikey.com/product-search/e ... 22-1995-ND

[Nils Roos]

Hi Rus,

I am still a little bit unclear about the intention of your post. Is this a proposal for a development project, and you are looking for developers?

[Talis9]

Needed to register again .. Site has a login issue & drops sessions . so prefer to use my email .. less a headache, this planet does not let u rest .. DO u have a trusted engineer in the US near SanFrancisco that can use 50GHz digital CRO + synthesizers ? HP Vector Analyzers, Tracking Gens .. all from Standards Lab .. need to locate these until i get there March 17.

Back on topic : JESD204D works with 3.072 G AND 5.333Gbps , a single lane up to IQ rates to 133.3MSPS and Dual Lane from 153MSPS up to 266MSPS , i have read on the Dev Sys notes the single / dual lane Xover point is 153.6MSPS .. p 51 of 91 on data sheet

As i need near maximum rate 220 MSPS or near to that based on SigmaDelta decimation filter requirement .. thus 2 lane operation

the real worry is the serializer PLL which has onchip controller based on IQ data rate , i dont know if the lock-in function can work over at least several MHz without the loop dropping out .. in an agile sweep that obviously needs to change sample rate if filter performance is to be utilized.

Of course i can sweep the LO simultaneous to the tracking gen .. (use 4351 given its excellent performance, low DC power and small size) keeping the sample rate stable , if it cant be swept slowly ( DDS ) This is one area where the digital demodulation provides feedforward to maintain lock-in of the synchronous receiver .. There is also reason for using 2 X 6676 devices (at variable Fc offset) Thus the need for DUAL FMC host FPGA

Plan is to use 2 standard AnalogDevices Eval 6676, replying on the FMC host for Demodulation function ( really a port to MatLAB ) yet Demodulation tweaking needs to be available and MatLAB does not do that , i note a node locked license comes with the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit .. I note the absence of buffers on the FMC lines and still looking if differential I/O is offered at the 300mV swing at 100ohm term spec of the 6676 .. Whilst the MALI is not the best GPU this is a much later assignment , First the basic return signal from the phosphorylation site needs to be converted .. this happens inside an electronmicroscope , ( the IF conversion) , so that stage is well shielded.

I check if theres something from Imagination Tech , they target FPGA and parallel processing very elegantly .. However the support tools are important .. the layout of the ZCU102 is a dogs breakfast around the FMC connectors , esp the DIP switches , not designed for 266MHz throughput

That is OK .. This board can serve as the motherboard IF IT CAN HOST 2 6676 Eval boards + handle DEMOD

Vivado design suite still requires the intelligence to create the code blocks ( which is what i ask of you ) Naturally with a tweakable I/F thru the Xilinix SDK or thru PetaLinux which is going to provide a " standard GUI " upgraded to suit the tweaks ( such as frequency / phase offset , etc ..

There are no developers capable of doing this much beyond yourself ( and a few AD staff ) , thus do i send the relevant hardware ? Thanx ,
Rus

[Talis9]

Its tempting to run with commercial products : for example this covers 950 -2200MHZ but the analog IQ is far from ideal, as is 12 bit A/D
https://forums.xilinx.com/t5/Xcell-Dail ... a-p/712313

or others with 16bit 4 channel A/D there is no ability to offset phase / frequency dynamically between channels , except in the digital downconverters Which is a bit late in a dual point front end. Great board tho , its designed for synthetic beam-array processing :

http://www.pentek.com/products/detail.cfm?model=71861 looks like the A/Ds share a common clock

A real help would be a library of programmable digital downconverters ..