Hopefully it is clear this project requires expertise in dynamic fabric design as well as HS bus validation of data across FMC circuits.
I plan2 modify ZCU102 FMC port adding differential buffers with adjustable duty cycle AND floating active threshold on the inverted pairs
One error source potential by way of rising bias with trailing 1's imposed on package lead capacitance by impedance mismatch & reflection of on chip junction detection , not in this example, but almost likely with the 6676 Eval to Analog Devices FMC host issues.
Frustration wth FMC differential I/O to Analog Devices Eval boards , greatly relaxed from AD6676 exist.
perhaps the more demanding dual lane mode 6676 is going to be a hard beast to tame in an agile spec.
Here is an example of a standard LVDS differential interface thru FMC with 5MSPS not 260MSPS as with the AD6676 :
I am trying to control the AD7960 evaluation board using an FPGA.
The output data seems wrong as can be seen in this screenshot (CH1 is CNV+, CH2 is D+, CH3 is DCO+)
All jumpers are at their default position.
Enable bits are EN2=0, EN1=0, EN0=1.
I'm not sure if REFIN is 0v or 2.048V. This is not clear in the evaluation board documentation.
The clock rate is 3MHz. This is to insure low noise. It is also harder to see higher frequencies on the scope.
The signals in the scope seem to have an amplitude of only 300mV. If I disconnect them from the FPGA, the amplitude is 1.8V.
The signals are connected to LVDS pins in the FPGA.
This is not indicative of the HS comm issues in 2 lane 6676 FMC interface, only an example of others FMC troubles.
Placement, modules, components and accessories; the ones that exist and the the nice-to-be's
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