Schematic V1.1

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Renegade243
Posts: 2
Joined: Fri Jan 20, 2017 11:11 am

Schematic V1.1

Post by Renegade243 » Fri Jan 20, 2017 11:15 am

Hi,

Is there a schematic available for V1.1 of the Red Pitaya, or has it been relatively unchanged since the first version V1.0 ?
I am asking because I am trying to give the RP an external clock but I am having difficulty in locating the correct resistors to de-solder and move. Help will be very much appreciated.

Thanks.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Schematic V1.1

Post by Nils Roos » Sun Jan 22, 2017 11:35 pm

Hi,

there are only minor differences between v1.0 and v1.1 and the resistors for the external clock selection are in the same place on both boards. On the top side, they are located under the input-facing corner of the heatsink (you have to remove the heatsink to access them).

Renegade243
Posts: 2
Joined: Fri Jan 20, 2017 11:11 am

Re: Schematic V1.1

Post by Renegade243 » Tue Jan 24, 2017 10:06 am

Thanks Nils!

However I have one more question, why can you not map a clock from the I/O pins using the clock wizard IP and have that serve as the master clock for the FPGA?

Edit: Observing the schematic shows that the clock is buffered through the ADC, so if the clock was delivered into the FPGA the ADC would not be synchronised on the same clock.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Schematic V1.1

Post by Nils Roos » Tue Jan 24, 2017 9:04 pm

Yeah, nothing is keeping you from deriving the FPGA clocks from a source on the IOs, but it is pointless to do it because the ADC will not operate on this clock unless rejumpered (=resoldered) to do so.

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