Use FPGA internal RAM for Feedforward

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Use FPGA internal RAM for Feedforward

Post by tzw » Wed Mar 01, 2017 9:47 am

Hey guys,

I would like to use the RP for doing Feedforward. The idea is to store the feedforward function values in the internal RAM. Depending on the given set point on the ADC I would like to give out a certain value of my feedforward function.
Question is now: How can I use the internal RAM in Verilog programming? A reference would be nice, where I can look up the internal modules of the Red Pitayas FPGA and how to use them.


Nils Roos
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Re: Use FPGA internal RAM for Feedforward

Post by Nils Roos » Wed Mar 01, 2017 9:46 pm

One of the easiest ways is to define a two dimensional register array, like the adc_a_buf here. If you do not violate certain constraints that the BRAM blocks have, Vivado will automatically implement this array in BRAM. The constraints are things like only two accesses per cycle (because the BRAM blocks are dual port).

You can also instantiate the BRAM_xxx_MACRO macros, which give you more fine-grained control over the configuration of each block, or use the block memory generator IP in a block design.

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