Poor clock output from FPGA

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Joined: Mon Nov 20, 2017 7:54 am

Poor clock output from FPGA

Post by viviantern » Mon Nov 20, 2017 8:09 am

I am using the N80960SB-10 Microprocessors from INTEL (http://www.kynix.com/Detail/8473/N80960SB-10.html) with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it was not as I expected.

FPGA Clock (system): 100 MHz Divider: 32 SPI Clock (output): 3.125 MHz

So I expect, a 320 ns cycle with 160 ns HIGH time and 160 ns LOW time. From the Simulation I get exactly what i expect. But using an oscilloscope at the PMOD output, I get a clock signal thats not too satisfactory. Also from the ADC datasheet (Pg. 10) the minimum high or low time should be 125 ns when working above 4.74 Vcc. Vcc in my case is 5V.

The high time is 132 ns at 3V level (HIGH) and and 144 ns at 0.8V level (LOW). The clock duration converges at 3.2V level. The expected time is 160 ns and I don't find any reason for the poor clock output.

Below diagram is a screen print of the oscilloscope.


Blue line: CLK Redline: CS

The reason I mark the values at 3V and 0.8V is as per theADC datasheet (Pg. 4) the Vih is from 3 to 5.5V and Vil is from -0.3 to 0.8V.

Please suggest a possible reason for the poor output from the FPGA and how do I improve the clock output?

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