V1.03 FPGA compiling projects

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awmlee
Posts: 5
Joined: Fri Dec 13, 2019 6:31 pm

V1.03 FPGA compiling projects

Post by awmlee » Fri Jun 19, 2020 7:56 pm

I just git cloned version 1.03 and tried compiling one of the projects. It produces a bit file that is 965 kB and *does not* work when copied to the RP /opt/redpitaya/fpga directory. The prebuilt files are all 2036 kB in size and *do* work when copied to same directory.

I only ran two lines of code:

git -clone https://github.com/RedPitaya/RedPitaya.git

and

c:\Xilinx\Vivado\2017.2\bin\vivado.bat -mode batch -source red_pitaya_vivado_Z10.tcl -tclargs streaming

There's so much data generated in the compilation, that it's difficult to see where it's failing. If an experienced user could give the top 3 trouble spots in compilation that would be of tremendous help.

A few things that look troubling :

1) From post_synth_timing_summary.rpt
TNS (total negative slack) -758.143 ns
2) From vivado.log:
WARNING: [Vivado 12-627] No clocks matched 'dac_clk_o'. [f:/temp/RedPitaya/fpga/sdc/red_pitaya.xdc:222]
3)from vivado.log:
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks dac_clk_o]'. [f:/temp/RedPitaya/fpga/sdc/red_pitaya.xdc:222]


edit:

Thinking that this was a windows issue, I installed Ubuntu 16.04 and Vivado 17.2 on a virtualbox. I did the same things as I did under windows:

git clone https://github.com/RedPitaya/RedPitaya.git

and generated a bitfile through the gui, which did not work:

/opt/Xilinx/Vivado/2017.2/vivado -source ./red_pitaya_vivado_project_Z10.tcl -tclargs streaming

and generated a bitfile through the command line, which did not work:

opt/Xilinx/Vivado/2017.2/bin/vivado -source ./red_pitaya_vivado_Z10.tcl -tclargs streaming

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