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"Bare Metal" programming on Red-Pitaya

Posted: Sat Sep 12, 2020 12:37 pm
by ThirdClassToaster
Hi, i had the following question.

The Red Pitaya has 2 interfaces that would technically be able to program the
Red Pitaya with Vivado "bare metal", i.e. without the inserted SD card with the Red Pitaya
operating system.
1) A micro USB socket with an FTDI chip behind it (named CON) on the back of the
2) A JTAG interface (pin header named JTAG) on the front side.

Is it possible to program the Red-Pitaya or the Zynq-SoC, i.e. both the PS and
the PL part, via one or even both of these interfaces "bare metal", or not ?

If it is possible, is there a cable that is officially or unofficially supported
and in any case works in combination with one of these two interfaces on the
Red-Pitaya ?

Best Regards

Re: "Bare Metal" programming on Red-Pitaya

Posted: Wed Sep 16, 2020 4:52 pm
by seba_jor
Hi, indeed you could program the red pitaya in a bare metal way.
I had used the Platform Cable USB II of xilinx and dont have any problems to upload bit files to the fpga and elf files to the arm cores using the xmd command line. Also I could run some other features like the ILA core in vivado.

Re: "Bare Metal" programming on Red-Pitaya

Posted: Mon Nov 16, 2020 2:56 pm
by redpitaya
You should be able to find the cable with the XIlinx.
Also check this resource for Bare metal programming information: ... la1k7Rz_yx

Re: "Bare Metal" programming on Red-Pitaya

Posted: Thu Nov 19, 2020 1:35 pm
by redpitaya
Black Friday 2020 is here!

Re: "Bare Metal" programming on Red-Pitaya

Posted: Sat Dec 19, 2020 7:36 pm
by AbdelmoumenBacetti
Please, add a tutorial for fpga synthesis on Windows.
All I have found so far is on Linux!!!!

Re: "Bare Metal" programming on Red-Pitaya

Posted: Sat Dec 19, 2020 8:08 pm
by AbdelmoumenBacetti
I was trying to replicate the process of creating a Vivado project on Windows but I got errors.
Here is the output from the command line.
D:\fpga>c:\Xilinx\Vivado\2019.1\bin\vivado.bat -mode batch -source red_pitaya_vivado_project_Z10.tcl -tclargs axi4lite

****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source red_pitaya_vivado_project_Z10.tcl
# set prj_name [lindex $argv 0]
# puts "Project name: $prj_name"
Project name: axi4lite
# cd prj/$prj_name
# set path_brd ../../brd
# set path_rtl rtl
# set path_ip ip
# set path_bd project/redpitaya.srcs/sources_1/bd/system/hdl
# set path_sdc ../../sdc
# set path_sdc_prj sdc
# set_param board.repoPaths [list $path_brd]
# set part xc7z010clg400-1
# create_project -part $part -force redpitaya ./project
create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 406.227 ; gain = 108.098
# source $path_ip/systemZ10.tcl
## namespace eval _tcl {
## proc get_script_folder {} {
## set script_path [file normalize [info script]]
## set script_folder [file dirname $script_path]
## return $script_folder
## }
## }
## variable script_folder
## set script_folder [_tcl::get_script_folder]
## set scripts_vivado_version 2020.1
## set current_vivado_version [version -short]
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
## puts ""
## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
## return 1
## }

WARNING: [Vivado 12-818] No files matched ''
# generate_target all [get_files]
# add_files ../../$path_rtl
# add_files $path_rtl
# add_files $path_bd
ERROR: [Vivado 12-172] File or Directory 'project/redpitaya.srcs/sources_1/bd/system/hdl' does not exist
INFO: [Common 17-206] Exiting Vivado at Sat Dec 19 20:03:44 2020...