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Drive adc clock from the fpga

Posted: Wed Sep 16, 2020 5:28 pm
by seba_jor
Hi, I know that you could drive the adc clock of the ADCs moving the resistors r25 and r26 to r27, r28.
But in the vivado side how you have to set the outputs??

I know the adcs clock are LVDS signal so I was thinking in generate the clock signal from the PS fclk feed it to a OBUFDS and set the output to the N20, P20.

The xdc file of the redpitaya github (also pavel's one) set N20, P20 as LVCMOS18, I tried to change it to LVDS_25 (is a hr bank) but this wouldnt work. So I use DIFF_HSTL_I_18 but I am not seeing a good behavior of the adc input clock port.

Looking at the LTC2145-14 datasheet it says that the adcs could work in a singled ended fashion, so I could use an oddr, tied the N20 to 0 and the adc still would be clocked?