LVDS or LVDS_25 capability
Posted: Mon Nov 15, 2021 6:34 pm
Dear RedPitaya team,
Can you advise on what differential signalling constraint be used to implement LVDS signalling on the PL I/O (E1) extension connector?
It appears as though the 3.3V Vcco prevents one from using the Zynq's internal differential termination i.e. DIFF_TERM=FALSE.
It seems from a previous reply that TMDS might work. Is this still the case? If that's the case am I just supposed to hack 50 ohm pull-ups from all the pins that I require differential signalling from?
And this termination should be Jerry-rigged at the E1 connectors correct?
If it is indeed the case that straight up LVDS (or even TMDS) cannot be used without such external intervention - then saying 'Differential signalling' on the schematic is incomplete. Some notes should be included on the details of how differential signalling may be implemented.
Opp
Can you advise on what differential signalling constraint be used to implement LVDS signalling on the PL I/O (E1) extension connector?
It appears as though the 3.3V Vcco prevents one from using the Zynq's internal differential termination i.e. DIFF_TERM=FALSE.
It seems from a previous reply that TMDS might work. Is this still the case? If that's the case am I just supposed to hack 50 ohm pull-ups from all the pins that I require differential signalling from?
And this termination should be Jerry-rigged at the E1 connectors correct?
If it is indeed the case that straight up LVDS (or even TMDS) cannot be used without such external intervention - then saying 'Differential signalling' on the schematic is incomplete. Some notes should be included on the details of how differential signalling may be implemented.
Opp