Redpitaya Forum

Hello

I'm new to FPGA and I'm studying programming the PL part of RP STEMlab 125.14 via Vivado 2020.1.
I'm currently doing a project that requires both output1 and output2. I can easily control the output2 because in the constraint file "ports.xdc" we have declared the 14 bits.
But how can I control the output1. I looked up in the datasheet, before the DB0-DB13 there are 14 red cross.
Is there a way to control the 14 bits output1?
Thank you very much

xum

Both outputs are controlled using the same bus (DAx pins). The catch is the inputs are configured as "interleaved mode" and operate at 250 MHz. For more info, see the DAC's datasheet (AD9767).

The solution for driving both channels in this mode is implemented in official FPGA images and you can have a look there.

juretrn wrote: ↑

Mon Jun 05, 2023 9:40 am

Both outputs are controlled using the same bus (DAx pins). The catch is the inputs are configured as "interleaved mode" and operate at 250 MHz. For more info, see the DAC's datasheet (AD9767).

The solution for driving both channels in this mode is implemented in official FPGA images and you can have a look there.

Thank you very much juretrn, I succeed in controlling the output1. Your advice helps a lot