125-14 4CH custom clock feature

[fbalakirev]

The developer guide for 125-14 4ch states:

Code: Select all

The internal ADC clock can be locked to an external reference clock via an extension connector (this feature is only available upon customer request).

It sounds as some sort of custom modification of the hardware that can be requested by the customers. Where can I find more info about the nature of this modification?

[redpitaya]

Hello fbalakierv,

Thank you for writing on the forum.

On the 4-Input version (STEMlab 125-14 4-Input board) you can switch between internal and external clocks by connecting the CLK_SEL pin to GND for the board to switch to EXT clock and to 3V3 (Vcc) to use the internal clock: https://redpitaya.readthedocs.io/en/lat ... tml#pinout

I will edit the documentation to be more clear regarding this.

The specified line refers to the option of modifying the board to require the external clock to operate (normally, the clock selection is done through the CLK_SEL pin, but we can modify the board to only work with the external clock)

I hope this helps

[fbalakirev]

Thank you for the clarification.

Would you happen to know what is the intended functionality of the pll_hi_o and pll_lo_o outputs? It appears that pll_hi_o and pll_lo_o were originally wired to the oscillator OE input, but now are disconnected from the oscillator chip in the current schematics. It seems that the intention was to shut the on-board oscillator off when ext clock is selected, but perhaps there other reasons to implement pll_hi_o and pll_lo_o?

[redpitaya]

The pll_lo_o and pll_hi_o are meant for VCXO oscillators, which can be tuned through voltage regulation. The functionality was implemented in case of modification requests (users wanted to have a VCXO), but the default oscillator on the Red Pitaya does not support this functionality (is a normal crystal oscillator).