Extension port as input

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tbet
Posts: 1
Joined: Thu Aug 07, 2014 1:27 pm

Extension port as input

Post by tbet » Thu Aug 07, 2014 1:36 pm

Hi,

I'm trying to use the digital IO on the extension port. It works fine as an output, but somehow I have issues to a dedicated port working as an input.
Here is the relevant part of my xdc-file for the Vivado design flow :

# Expansion connector
set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}]
#set_property SLEW FAST [get_ports {exp_p_io[*]}]
set_property SLEW FAST [get_ports {exp_n_io[*]}]
#set_property DRIVE 8 [get_ports {exp_p_io[*]}]
set_property DRIVE 8 [get_ports {exp_n_io[*]}]

set_property IOB TRUE [get_ports {exp_p_io[0]}]

set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}]
set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}]
set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}]
set_property PACKAGE_PIN H17 [get_ports {exp_n_io[1]}]
set_property PACKAGE_PIN H18 [get_ports {exp_n_io[2]}]
set_property PACKAGE_PIN K18 [get_ports {exp_n_io[3]}]


Alll exp_p_io are/should be declared as inputs and all exp_n_io as outputs.

I have now just implemented a mapping in VHDL like :

exp_n_io(3) <= exp_p_io(0);

,i.e. the signal on the input port exp_p_io(0) should just be regenerated on the output exp_n_io(3).
To my regret this doesn't seem to work - any suggestions/hints if there could be some external driver on the redpitaya board blocking the access to the FPGA pin - or if this is a different issue ?

Crt Valentincic
Posts: 67
Joined: Wed May 28, 2014 12:15 pm

Re: Extension port as input

Post by Crt Valentincic » Mon Aug 18, 2014 9:59 am

All the connections from FGPA to extension connectors are direct (http://wiki.redpitaya.com/index.php?tit ... _connecors).

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