Page 1 of 1
Differential IO Standards on E1/E2 Connectors
Posted: Wed Jun 18, 2014 3:48 pm
by Crt Valentincic
Originally posted by Tom Gardner:
Which differential input and output standards can be used for inputs and outputs on the E1 and E2 connectors.
I'm particularly interested in (1) differential standards for high speed IO, and (2) what differential terminations exist on the board or can be used in the Zynq.
I guess Vcco is fixed at 3.3V, but what about Vref? If I understand the Zynq literature, 3.3V implies both LVDS and internal differential terminations are impossible.
A schematic would, of course answer (2) unambiguously!
Re: Differential IO Standards on E1/E2 Connectors
Posted: Wed Jun 18, 2014 3:48 pm
by Crt Valentincic
We would suggest you to use TMDS_33 or LVCMOS. All GPIO pins are connected directly to FPGA and there are no terminations on the Red Pitaya itself. Vref cannot be used.
Re: Differential IO Standards on E1/E2 Connectors
Posted: Wed Jun 18, 2014 10:14 pm
by tggzzz
LVCMOS is not a differential IO standard.
I do not see how TMDS_33 can be used without unacceptable signal integrity problems since, according to ug471 "7 Series FPGAs SelectIO Resources User Guide", p95
The TMDS standard requires external 50Ω pull-up resistors to 3.3V on the inputs
I suggest you remove references to differential signalling on the E1/E2 connectors and explicitly state which standards can be used (presumably LVTTL is allowed).
Re: Differential IO Standards on E1/E2 Connectors
Posted: Mon Jun 23, 2014 2:41 pm
by Crt Valentincic
TMDS_33 should work fine also if you put 50 ohm pull-ups near extension connector and there is also a possibility to create differential interface by use of complementary LVTTL or LVCMOS logic. Can you provide more information about what are you going to connect to these IOs?
Re: Differential IO Standards on E1/E2 Connectors
Posted: Wed Jul 02, 2014 1:25 pm
by tggzzz
My basic requirement is to get a few high speed signals into the Zynq's PL fabric, capture them and use a combination of PL and PS to analyse them.
The data sources for such high speed signals are typically some differential ECL variant, such as PECL or LVDS. Since the rise/fall times can be 250ps or less, signal integrity becomes an issue if pattern-sensitivity problems are to be avoided. Arguably even for non-ECL signals, it is prudent to assume sub-nanosecond rise times (I first encountered such risetimes 20 years ago!)
I am currently experimenting with a MicroZed and a custom external carrier board to determine the maximum bit rate possible; I hope to exceed 1Gb/s. The main reason I chose the MicroZed is that it has a very good physical IO structure designed to minimise signal integrity issues, e.g. high speed connectors (which are less easy to "use" than 0.1" headers), and one ground for every two signals, evenly distributed along the connector, and uncommitted Vccio voltage. I will be using the Zynq PL fabric's built-in terminations for LVDS signals.
Part of the application I have in mind would be a useful adjunct to the Red Pitaya's main function, and so I am curious whether it would be possible to use the Red Pitaya. The major stumbling blocks I have identified are:
- Vccio=3.3V so cannot use built-in termination - thus external termination is mandatory
- TMDS could be used instead of LVDS, if terminated correctly
- distribution of grounds on the E1/E2 connector is probably adequate for one (possibly two) differential pairs
- the rule-of-thumb for unterminated tracks is that they will not cause problems if the length is less than 1/6 the signal's risetime. An off-board termination plus a 30mm on-board unterninated track would be OK for signals with, say, >900ps risetime. N.B. I have not verified that by simulation.
Unfortunately, therefore, 50ohm terminations on the external board are unlikely to be adequate for my application, unless system performance is reduced.
As far as I can see, the Zynq does not have IO structures supporting differential TTL/CMOS signals, so I would be grateful if you could indicate your strategy for using complementary TTL/CMOS signals. I have not yet seriously considered whether it is beneficial to synthesise differential TTL/CMOS from two single-ended signals.
Nonetheless, congratulations on getting the Red Pitaya into production - it cannot satisfy all requirements, and "the best is the enemy of the good"
Re: Differential IO Standards on E1/E2 Connectors
Posted: Wed Jul 16, 2014 11:46 pm
by dpryan
Hi tggzzz -- I'm looking to do something similar. How about using the SATA connectors on the Red Pitaya? I can't find a hardware schematic to verify, but from what I'm reading in the documentation, those connectors provide two differential pairs each.
Re: Differential IO Standards on E1/E2 Connectors
Posted: Thu Jul 17, 2014 1:04 am
by tggzzz
Could the SATA connectors be used? I don't know, so this is mere speculation...
The SATA connectors are intended to allow multiple Red Pitayas to be daisy-chained together, Clearly that functionality would be lost, and it would also be necessary to change/remove the Zynq PL code to avoid conflicting with your use of the SATA connectors. I have not looked to see if that is practical.
It is also necessary to have appropriate termination and PCB layout. I don't think the hardware definition has been released; the only information available is the PL source code. In file
https://github.com/RedPitaya/RedPitaya/ ... ya_daisy.v
we see
Code: Select all
OBUFDS #(.IOSTANDARD ("DIFF_SSTL18_I"), .SLEW ("FAST")) i_OBUF_clk
(
.O ( daisy_p_o[1] ),
.OB ( daisy_n_o[1] ),
.I ( txs_clk )
);
IBUFGDS #(.IOSTANDARD ("DIFF_SSTL18_I")) i_IBUFGDS_clk
(
.I ( daisy_p_i[1] ),
.IB ( daisy_n_i[1] ),
.O ( rxs_clk )
);
IBUFDS #(.DIFF_TERM ("FALSE"), .IOSTANDARD ("DIFF_SSTL18_I")) i_IBUFDS_dat
(
.I ( daisy_p_i[0] ),
.IB ( daisy_n_i[0] ),
.O ( rxs_dat )
);
so perhaps it is possible.
(Q: why does one input have "DIFF_TERM ("FALSE"),"?