Hello Nils,
Thanks for the information. I can see that the v0.96 release has added AXI4 bus and DMA to the external buffer. I can use the v0.96 pre-release code in my design as long as it is marginally stable. Who will be the right person with more information about the v0.96 release?
Regards,
Bhaskar.
Bus speed FPGA core - DDR3 Ram
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Re: Bus speed FPGA core - DDR3 Ram
You could try contacting forum user izi. He is the FPGA developer at Red PItaya.
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Re: Bus speed FPGA core - DDR3 Ram
Thanks for the help Nils. I checked out the v0.96 code and it seems that the DAC stream handling is still under development. The signal generator block still has an internal BRAM to store samples for the DAC.
I will contact izi for futher help.
Bhaskar.
I will contact izi for futher help.
Bhaskar.
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