Bus speed FPGA core - DDR3 Ram

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wa4557
Posts: 7
Joined: Thu Oct 23, 2014 9:57 pm

Bus speed FPGA core - DDR3 Ram

Post by wa4557 » Tue Nov 11, 2014 2:38 pm

Hey all,

I'm trying to build an arbitrary waveform generator using the RedPitaya and its external trigger pin. Everything works so far, but in order to increase the amounts of different pulses I need to store them in the RAM (basically a big C-array) and write them on the fly to the FPGA core.

The speed however with which I can write to the samples from the RAM to the FPGA data buffer is something like 6.6ms for 16k samples, which is rather slow for my purposes.
Reading a value from a register takes something like 200ns which is also well below the specs...

Shouldn't it be possible to write/read with speeds up to 200MHz? Can we set something like priorities in the OS to increase the maximum transfer rates?

Thanks

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Tue Nov 11, 2014 7:55 pm

Hi, and welcome to the club (of people who need faster rates of transfer between the BRAM buffers and DDR3 RAM)
Shouldn't it be possible to write/read with speeds up to 200MHz?
No, the AXI general purpose master interface to which the RedPitaya's FPGA hardware is connected is clocked at 125MHz (FCLK[0]). The FPGA logic shares it with most other on-chip peripherals.
Add to that the facts that the internal FPGA system bus only supports single transfers (no bursts) and needs to do clock synchronisation for all accesses to the ADC-clock domain (ie the blocks scope, asg, pid) and you can see why it is not a good solution for fast transfers.
To quote the Xilinx tech ref manual (Chapter 5.5) re AXI_GP interfaces:
These interfaces are for general-purpose use only and are not intended to achieve high performance.
I know it's a shameless self-plug, but if you take a look at this project, you'll see I am working on a solution that bypasses this bottleneck and transfers data between the BRAM buffers and DDR3 RAM in a DMA-like fashion. It uses an AXI_HP interface, which IS intended to achieve high performance.
The path scope->DDR is nearly finished, DDR->asg is currently in development, interrupt support has not yet been started.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Tue Nov 11, 2014 8:26 pm

Oh, and should you have experience with the linux kernel, I would very much like to hear an expert's opinion on some matters of memory management and interrupts.

wa4557
Posts: 7
Joined: Thu Oct 23, 2014 9:57 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by wa4557 » Wed Nov 12, 2014 11:53 am

Good to know thanks!

So what are the speeds are achievable using the AXI_HP interface? Faster than the interal 125MHz of the DAC/DAC?

P.s: I'm afraid I'm by no means an expert for the Linux kernel, definitely less than you are; Thus I might be no big help here, sorry!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Wed Nov 12, 2014 1:13 pm

The AXI HP interface in my module is set up to transfer 64bit data at 125MHz in full duplex.

I have not yet tested the actual performance in full duplex (because the path DDR-to-generator is not yet fully functional), but writing both scope channels to DDR at full speed works without problems.

RobMorris84
Posts: 2
Joined: Thu Dec 04, 2014 3:30 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by RobMorris84 » Thu Dec 04, 2014 3:34 pm

Hi all,

Did anyone manage to get this working in the end? We're looking to do the same thing here (but with very limited experience of FPGA programming) and wondered if you had made any progress?

Thanks

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Thu Dec 04, 2014 8:41 pm

I am still at it. Writing ADC data to RAM is working fine, transferring samples from RAM to DAC suffers from some hickups, but I'm getting there.

RobMorris84
Posts: 2
Joined: Thu Dec 04, 2014 3:30 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by RobMorris84 » Thu Dec 04, 2014 10:28 pm

Thank you. Sounds like it is quite a challenge! Looking forward to seeing the results.

bhaskarm
Posts: 6
Joined: Sat Jul 16, 2016 6:48 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by bhaskarm » Sun Aug 14, 2016 10:36 pm

Hello Nils,
I was also interested in a high speed datapath from the external RAM to the DAC using the AXI HP bus. Were you able to finish this RAM to DAC code that you were working on? If it is still under development then I can help you in finishing it.

Thanks,
Bhaskar.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Mon Aug 15, 2016 9:22 pm

Hi Bhaskar,

development on that has been on hold for more than a year - I didn't have a usecase so it dropped out of sight.

You are very welcome to take a look at what is there (fpga project directory, in particular axi_master.v, red_pitaya_asg._v, red_pitaya_asg_ch._v), but it is now quite a bit outdated (eg. Vivado 2014.2). If you want to discuss this further, feel free to email me.

In the Red Pitaya master, there are provisions for DAC stream handling, but I am not sure of their current status.

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