Hardware Questions

[JamesMayf]

Hi all, I'm a final year electronics student trying to complete my final year project with the RedPitaya. I'm trying to create a piece of ultrasonic testing equipment capable of pulse echo and through transmission mode. I've already created the analogue front end and now I need to get started with the signal processing aspect. My questions at the moment are:

1. Am I correct in thinking that buffer used for the generate utility is the BRAM and as such has a size of 256kB?

2. Equalizatioon is refering to low pass filtering and shaping refers to high pass filtering?

3. What is the sampling limit for acquire and is the averaging done in hardware?

Please advise, it will be greatly appreciated

James

[john k2ox]

The details to your questions can be determined by looking at the verilog code available on github. The authors did a nice job of placing descriptions in the headers of the files.

Equalization is used to correct for frequency response errors. In this case due to the hardware, input amp and adc.

john

[Nils Roos]

Hi James,
To elaborate a bit on John's comments:

1. Am I correct in thinking that buffer used for the generate utility is the BRAM and as such has a size of 256kB?

The buffer for waveforn generation is in BRAM (which is not the same as the 256kB on-chip-memory) and has a size of 16k samples (=32kB) for each channel.

The generate utility loads the precomputed waveform into that buffer and then programs the ASG module with a step-size and wrap address to generate the waveform at the desired frequency. Both parameters have sub-sample resolution (1/64k - 16k), so you can achieve a wide range of frequencies with one waveform pattern and little processing overhead.

3. What is the sampling limit for acquire and is the averaging done in hardware?

acquire is - at the moment - limited by the speed with which you can get data out of the ADC's BRAM buffers. The maximum sustainable rate of reading data seems to be on the order of 2-4MSps.
Averaging is done in hardware, when you set a decimation factor and enable averaging, the ADC buffer will be filled with averaged data at the decimated rate.

If that rate is not enough for you, or if you need the CPU for other things besides copying data, I can offer you an alternative in the form of a modified FPGA which transfers ADC data to main memory in DMA mode. Drop me a note for details.