Output Serializer

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_undex
Posts: 6
Joined: Thu Dec 18, 2014 1:20 pm

Output Serializer

Post by _undex » Sat Dec 27, 2014 2:54 pm

Hi folks,

I'm trying to create a high frequency puls generator with the RP. By "high frequency" I mean more than 500 MHz. The more the better.
This puls signal should be customizable and should change over time, so I'm not looking for a PWM.

Anyway, I already made the DMA part working, the only thing I need now is a hardware serializer. I know I could just code one myself in VHDL/Verilog,
but this would decrease the performance in relation to an already integrated serializer.

I think I can't use the main two output ports of this board, as they're connected to a DAC, which I think one could not bypass. So the only option I have is to use a GPIO Pin or
to use an already existing highspeed port like SATA.

Does someone know a way to accomplish this task? The main question here is if there exists a hardware serializer on the Zynq-chip which i can utilise.

john k2ox
Posts: 39
Joined: Sun Oct 05, 2014 6:47 pm
Location: New York
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Re: Output Serializer

Post by john k2ox » Mon Dec 29, 2014 1:27 am

500 MHz? The DAC is clocked at 125 MHz with al low pass filter cutoff around 55 MHz.

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Output Serializer

Post by Nils Roos » Mon Dec 29, 2014 4:19 pm

Hi _undex,

I guess the OSERDESE2 logic is what you are looking for. Basically every IO pin is equipped with such a block; to use it, instantiate the macro of the same name (see for example red_pitaya_daisy_tx.v) and wire it to the appropriate exp_n/p_io. More info regarding the capabilities of the IO pins can be found here (pdf).

You will probably want to generate a seperate clock for this output. To do that, instantiate and configure the remaining free PLL and connect it to your serializer.
I am not sure if you will be able to reach 500MHz that way, the connections between the ZYNQ and the expansion connectors are not meant to carry HF - and neither is the connector itself well suited for that frequency range.

Maybe it is a better idea to repurpose the daisy chain interface. You'd still need to generate the desired clock via a new PLL, but the SERDES blocks are already in place and the external wiring is designed for HF use.

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