red_pitaya_analog.v dac_dat bit interpretation

[trollhassel]

Hi. Newbie question here:)

I am trying to make a pulse generator by modifying the output to the DAC. I simply set up code to send the signal to the DAC for the amount of clock cycles I desired followed by a pause where I send to the dac_dat_a and dac_dat_b ->
14'b10000000000000. (This generates a 0 Voltage during the pause which is needed).

This works fine. However, the further the pulse begins away from 0 voltage the greater the distortion to the signal is. So what I need to do is to find a range in dac_dat_a_i from a little above 0 voltage to a little below 0 voltage.

My problem is that I am having a hard time understanding the bit representation.

Can anyone help me by giving an example of how the bits in dac_dat_a_i are set?

What I want to achieve is an if-sentence similar to this:
if (dac_dat_a_i > - 10 && dac_dat_a_i < 10) begin
--- generate the pulse
end

So, to clarify; what values would "-10" and "10" need to be to find out if the signal is close to 0?

Thanks,

Hans-Kristian.

[pavel-demin]

The data types in Verilog are unsigned by default.

The solution is to use the $signed function or to define wires and registers as signed.

I'd say that the following should work:

if ($signed(dac_dat_a_i) > $signed(-10) && $signed(dac_dat_a_i) < $signed(10)) begin
--- generate the pulse
end

You can find a more detailed explanation at

http://excamera.com/sphinx/fpga-verilog-sign.html

[Nils Roos]

The bit representation that is used for DAC data is called two's complement. As Pavel said, the Verilog "$signed" keyword helps to deal with data in that representation.

[trollhassel]

Thank you for fast replies. I have one more question. I am using the signal generator to send a sine wave with four periods, then a short stop. The problem now, is that I need it to start sending out waves when sine wave amplitude is at zero and increasing. Therefor I need to know the values in the dac_dat_a_i register for a sine wave when it have negative amplitude, so I may start sending the sine wave only when the sine wave amplitude is increasing from zero.

[Nils Roos]

One way to do that would be to store the current dac_dat_a_i value in a register and compare that register's value to the current value.

Code: Select all

reg [14-1:0] dac_dat_old;

always @(posedge dac_clk) begin
    if (!dac_rst) begin
        dac_dat_old <= 14'h0;
    end else begin
        dac_dat_old <= dac_dat_a_i;
        if ($signed(dac_dat_old) <= 0 & $signed(dac_dat_a_i) > 0) begin
            // do stuff
        end
    end
end

[trollhassel]

Thank you for the help guys it is much appreciated! I just had to get rid of some stupidity, and now it works as I want it to. The $signed keyword and understanding 2's complement was what I needed.

In case it is of interest for anyone I post my code here:

By modifying red_pitaya_analog.v like this I can now run the "generate" in the terminal and get a pulse signal. It is now just set to a constant 1600 periodic signal where 4 periods are of the actual signal coming from the ASG and the rest of the periods "0" is sent to the DAC. The code is probably really messy and ugly for more experienced programmers, but it works

Another note: When the signal is output on channel 1 a signal that can be used as a trigger signal is sent on channel 2.

Code: Select all

reg  [14-1: 0] dac_dat_a  ;
reg  [14-1: 0] dac_dat_b  ;
reg  [14-1: 0] anti_osc = 0;
integer pos = 0'b0;
integer per = 0;
integer checkBit = 1'b0;

// output registers + signed to unsigned (also to negative slope)
always @(posedge dac_clk) begin  //CLK 125MHz
	// Code to keep track of periods
	if ($signed(dac_dat_a_i) > $signed(50) && pos == 0) begin // Checking if signal is above 0
		pos = 1;
        if (per == 1600) begin
            per = 0;
            checkBit = 0;
        end
	end
	if ($signed(dac_dat_a_i) < $signed(-50) && pos == 1) begin // Checking if signal is below 0. If so, period counter increments. 
		pos = 0;
		per = per + 1;
	end
	// per is now incrementing each period at the bottom slope.
	
	// Code to recognize a position close to 0
    if ($signed(dac_dat_a_i)>=$signed(0) && per == 5) begin
        checkBit = 1;
    end
	// checkBit is set to 1 when the signal is close to 0.
    
	// Code to receive data from buffer 
	if (per < 9 && checkBit == 1) begin  
		dac_dat_a <= {dac_dat_a_i[14-1], ~dac_dat_a_i[14-2:0]}; 
		dac_dat_b <= 14'b00000000000000; 
		dac_rst   <= !dac_locked;
	end
	else if (per == 9 && ($signed(dac_dat_a_i) < $signed(-100))) begin  
		dac_dat_a <= {dac_dat_a_i[14-1], ~dac_dat_a_i[14-2:0]}; 
		dac_dat_b <= 14'b00000000000000; 
		dac_rst   <= !dac_locked;
	end
	// Receives data from buffer for 4 periods	

	// Begin pause interval after 4 periods
	else if (per == 9 && $signed(dac_dat_a_i) >= -100) begin  		
		dac_dat_a <= 14'b01111111111111; 		
    	dac_dat_b <= 14'b01111111111111; 
		dac_rst   <= !dac_locked;
	end
	else if (per >= 9) begin      
		dac_dat_a <= 14'b01111111111111; 		
		dac_dat_b <= 14'b01111111111111; 
		dac_rst   <= !dac_locked;
	end
	
	else begin
		dac_dat_a <= 14'b01111111111111;   		
    	dac_dat_b <= 14'b01111111111111; 
    	dac_rst   <= !dac_locked;	
	end
end